Nonvolatile semiconductor memory device

ABSTRACT

With a local self boost (LSB) technique, the distribution of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a nonvolatile semiconductormemory and particularly relates to an electrically rewritablenonvolatile semiconductor memory (EEPROM, flash memory) employing memorycells each having a stack of a floating gate (charge accumulation layer)and a control gate.

[0002] The present invention also relates to a nonvolatile semiconductormemory utilizing a multilevel storage technique.

[0003] There is conventionally known, as a nonvolatile semiconductormemory which is electrically rewritable and capable of realizing highintegration, an NAND type EEPROM having a plurality of memory cellsmutually connected in series.

[0004]FIG. 1A is a plan view showing one NAND cell formed on a memorycell array on an EEPROM chip and FIG. 1B is an equivalent circuitthereof. FIG. 2A is a cross-sectional view taken along the line 2A-2A ofFIG. 1A.

[0005]FIG. 2B is a cross-sectional view showing one example of a crosssection taken along the line 2B-2B of FIG. 1A and particularly shows acase of employing an LOCOS element isolation film (312).

[0006]FIG. 3 is a cross-sectional view showing another example of across section taken along the line 2B-2B of FIG. 1A and particularlyshows a case of employing a trench element isolation insulating film(322). It is noted that a portion surrounded by a dashed linecorresponds to the portion shown in FIG. 2B.

[0007] As shown in FIGS. 1A, 2A, 2B and 3, a memory cell arrayconsisting of a plurality of NAND cells are formed on a P type siliconsubstrate (or P type well which will be referred to as herein) 311surrounded by the element isolation oxide film 312. One NAND cellincludes, for example, eight memory cells MC (MC1 to MC8) mutuallyconnected in series.

[0008] Each memory cell MC has a stacked gate structure. The stackedgate structure consists of an insulating film 313 formed on the P typewell 311, a floating gate 314 (314 ₁ to 314 ₈) formed on the insulatingfilm 313, an insulating film 315 formed on the floating gate 314 and acontrol gate (CG) 316 (316 ₁ to 316 ₈ or CG1 to CG8) formed on theinsulating film 315.

[0009] An N⁺ diffused layer (source/drain region) 319 of one memory cellMC is shared with its adjacent memory cell MC, whereby, for example,eight memory cells MC are connected to one another in series and oneNAND cell is formed.

[0010] One end of a current path of the NAND cell is connected to a bitline BL (318) through a drain-side select gate transistor ST1 and theother end thereof is connected to a source line SL through a source-sideselect gate transistor ST2.

[0011] The gate electrode of each of the select gate transistors ST1 andST2 has a structure in which the floating gate 314 (314 ₉, 314 ₁₀) andthe control gate 316 (316 ₉, 316 ₁₀), for example, are electricallyconnected with each other at a portion which is not shown.

[0012] The P type well 311, on which memory cells MC, the select gatetransistors ST1, ST2 and the like are formed, is covered with a CVDoxide film 317 or the like. The bit line (BL) 318 is arranged on the CVDoxide film 317. The bit line (BL) 318 extends in column direction.

[0013] The control gate CG (CG1 to CG8) of each memory cell MC is sharedamong NAND cells arranged in row direction and functions as a word lineWL (WL1 to WL8). The row direction is a direction orthogonal to thecolumn direction.

[0014] The gate electrode (314 ₉, 316 ₉) of the drain-side select gatetransistor ST1 is shared among drain-side select gate transistors ST1arranged in row direction and functions as a drain-side select gate lineSGD.

[0015] The gate electrode (314 ₁₀, 316 ₁₀) of the source-side selectgate transistor ST2 is shared among source-side gate transistors ST2arranged in row direction and functions as a source-side select gateline SGS.

[0016] The data stored by one memory cell MC in the NAND cell ismultilevel, i.e., binary or more.

[0017] In case of storing binary data, the range of the possiblethreshold voltages of the memory cells MC is divided into two typeswhich are assigned data “1” and “0”, respectively. In case of the NANDtype memory, the threshold voltages after data erase are normally“negative” and defined as, for example, “1”. The threshold voltagesafter data write are normally “positive” and defined as “0”.

[0018] In case of storing multilevel data, e.g., four-level data, therange of the possible threshold voltages of the memory cells MC isdivided into four types, which are assigned data “11”, “10”, “01” and“00”, respectively. In case the NAND type memory, the threshold voltagesafter data erase are normally “negative” and defined as “11”. Thethreshold voltages after data write are normally “positive” and definedas “10”, “01” and “00” in the order in which threshold voltages arehigher.

[0019] It is not always necessary that only the data after data erasehave “negative” threshold voltages. It suffices that the range of thepossible threshold voltages of memory cells MC is divided into aplurality of types. It also suffices that the polarity of a thresholdvoltage, i.e., whether the threshold voltage is “negative” or“positive”, is opposite to that described above.

[0020] In the data write operation technique of such an NAND typeEEPROM, a local self boost technique (LSB technique) is recentlyregarded as a favorable one. The operation of the NAND type EEPROMadopting the LSB technique will be described hereinafter with referenceto FIG. 1B.

[0021] (Data Erase Operation)

[0022] Data erase is roughly divided into two ways, i.e., batch eraseand block erase.

[0023] In batch erase, the data of all the memory cells MC existing onthe memory cell array are simultaneously erased. In this case, thepotentials of all the control gates CG (word lines WL) on the memorycell array are set at 0V, the bit lines BL and the source lines SL areturned into a floating state, respectively and then a high voltage(e.g., 20V) is applied to the P type well 311. By doing so, electronsare discharged into the P type well 311 from the floating gates 314 ofall the memory cells MC existing in the memory cell array and thethreshold voltages of all the memory cells MC are shifted in negativedirection.

[0024] In block erase, the data of the memory cells MC existing on thememory cell array are erased in units of blocks. Normally, one blockconsists of a group of NAND cells which are arranged in row directionand which share control gates CG (word lines WL). In this case, thepotentials of the control gates CG (word lines WL) in a select block areset at 0V, a high voltage (e.g., 20V) is applied to control gates CG(word lines WL) in non-select blocks, the bit lines BL and the sourcelines SL are turned into a floating state, respectively and a highvoltage (e.g., 20V) is applied to the P type well 311. By doing so,electrons are discharged from the floating gates 314 of the memory cellsMC existing in the select block into the P type well 31 and thethreshold voltages of the memory cells MC in the select block areshifted in negative direction.

[0025] The above-stated data erase operation is executed prior to thedata write operation to be conducted to the entire memory cell array orthe data write operation to be conducted in block units.

[0026] (Data Write Operation (LSB Technique))

[0027] Before starting the description of the data write operation, itis assumed that a select control gate CG in the select block is “CG2(word line WL2)”.

[0028] In the data write operation, a predetermined positive voltageVsgd is applied to a select gate line SGD in a select block and 0V isapplied to a select gate line SGS. Also, 0V is applied to all word linesWL and all select gate lines SGD and SGS in non-select blocks.

[0029] In this state, if data write is carried out by means of the LSBtechnique, the select word line WL2 is applied with a high voltage Vppfor data write, non-select word lines WL1 and WL3 adjacent to the selectword line WL2 are applied with 0V, respectively, and non-select wordlines WL4 to WL8 other than the non-select word lines WL1 and WL3 areapplied with a voltage Vpass, respectively. The voltage Vpass is almostin the middle of 0V and the data write high voltage Vpp. Although 0V isapplied to the non-select word lines WL1 and WL3 in the above example, apositive voltage lower than Vpass may be applied thereto.

[0030] Data write is normally carried out sequentially from the memorycell MC8 farthest from the bit line BL toward the memory cell MC1closest thereto.

[0031] (Data “0” Write)

[0032] When data “0” (or data having a “positive” threshold voltage inthis example) is written, 0V (write select voltage) is applied to aselect bit line BL.

[0033] The data of the memory cell MC1 closer to the bit line BL thanthe select memory cell MC2 is always in an erase state (which data has a“negative” threshold voltage in this example). Due to this, even if thevoltage of the word line WL1 is set at 0V, the voltage of 0V applied tothe bit line BL is transferred to the channel of the select memory cellMC2 and to an N⁺ type diffused layer 319 thereof. As a result, in theselect memory cell MC2, electrons move from the P type well 311 to thefloating gate 314 and the threshold voltage of the select memory cellMC2 is shifted in the positive direction.

[0034] (Data “1” Write)

[0035] When data “1” (or data having a “negative” threshold voltage inthis example) is written, a voltage (write non-select voltage) equal toor higher than the voltage Vsgd is applied to the select bit line BL.

[0036] Here, the select gate SGD is applied with the voltage Vsgd. Dueto this, the select gate transistor ST1 becomes non-conductive and thechannels and N⁺ type diffused layers 319 of the memory cells MC1 to MC8are turned into a “floating state”, respectively. In this state, if thewrite high voltage Vpp and the voltage Vpass are applied to the selectword line WL2 and to the non-select word lines WL4 to WL8 other than thenon-select word lines WL1 and WL3, respectively, then the channelpotential of the select memory cell MC2 and those of the non-selectmemory cells MC4 to MC8 as well as the potentials of the N⁺ typediffused layers 319 are increased.

[0037] The memory cells MC1 and MC3 adjacent to the select memory cellMC2 are cut off by the back-bias effect caused by the increased channelpotentials. At this moment, the high voltage Vpp is applied to thecontrol gate CG2 (word line WL2) of the select memory cell MC2. Thus,the channel potential of the select memory cell MC2 is increasedfurther. The channel potential of the select memory cell MC2 rises toabout 8 to 9V if the high voltage Vpp is, for example, 18V and a channelboost ratio is 0.5. Namely, the potential difference between the wordline WL2 and the channel of the select memory cell MC2 is decreased to avalue sufficient to provide a write inhibit voltage. As a result, in theselect memory cell MC2, there is little movement of electrons from the Ptype well 311 to the floating gate 314 and the threshold voltage of theselect memory cell MC2 is kept “negative”.

[0038] (Data Read Operation)

[0039] In data read operation, a voltage (e.g., 3.5V) for continuity isapplied to the select gate lines SGD and SGS in the select block and tothe control gates CG (word lines WL) of the non-select memory cells. Bydoing so, the select gate transistors ST1 and ST2 in the select blockand the non-select memory cells are turned “on”. In this state, a readvoltage of 0V or the like is applied to the control gate CG (word lineWL) of the select memory cell in the select block. At this moment, thepotential of the bit line BL is changed according to a current flowingthereto through the select memory cell. Whether data is data “1” or “0”is determined by detecting the changed bit line potential. In case ofstoring four-level data, it is determined whether the data is data “11”,“10”, “01” or “00”.

[0040] As described above, in data write operation employing the LSBtechnique, a voltage not less than 0V and less than Vpass is applied tonon-select word lines adjacent to a select word line which is appliedwith a high voltage, and the voltage Vpass is applied to the remainingnon-select word lines.

[0041] With such an LSB technique, it is possible to increase thechannel potential of the select memory cell, thus occurrences forwriting errors at the time of particularly writing data “1” can besuppressed. Besides, since the variation of the threshold voltages ofcells becomes quite small, the LSB technique is regarded as a favorableone particularly for writing data to a multilevel memory.

[0042] Nevertheless, problems are rising in the LSB technique as cellsare made smaller in size and higher integration progresses.

[0043] The greatest feature of the LSB technique is that non-selectmemory cells adjacent to a select memory cell must be turned into acutoff state irrespectively of the data stored in these non-selectmemory cells. The non-select memory cells adjacent to the select memorycell have arbitrary threshold voltages. owing to this, there are caseswhere one of the adjacent non-select memory cells has a “positive”threshold voltage or both of them have “negative” threshold voltages(erase state).

[0044] To cut off these adjacent non-select memory cells by means of theback-bias effect caused by the channel potential, it is necessary tosufficiently increase the voltage Vpass or to control threshold voltagedistribution after data erase to thereby sufficiently increase thelowest threshold voltage.

[0045] As regard the former case, to suppress the voltage Vpass-inducedvariation of the threshold voltages of the non-select memory cellsconnected to the non-select word lines and to the selected bit line, thevoltage Vpass cannot be set so high. To the contrary, the lower thevoltage Vpass, the more effectively the threshold voltage variation ofthe non-select memory cells can be suppressed and writing error can beprevented. Considering this, therefore, it is essential to set thethreshold voltage distribution after data erase to be higher within therange in which the erase state can be read and to sufficiently narrowthe distribution width.

[0046] It is necessary that the distribution width of the thresholdvoltage after erase is limited within the range of, for example, “−3V to−0.5V”.

[0047] In these circumstances, the present applicant proposed a softwrite technique. The soft write technique is to gradually write data ona memory cell after erasing data and to gradually move the thresholdvoltage of the memory cell in positive direction. To be specific, afterdata is erased, using a sufficiently low voltage as a start voltage, awrite pulse is applied to word lines for each block while repeatedlystepping up the start voltage and conducting verification for eachblock. This makes it possible to greatly narrow the distribution widthof the threshold voltages after data erase.

[0048] The write operation in an NAND type EEPROM by means of the LSBtechnique and a technique for controlling a threshold voltagedistribution after data erase by means of the soft write technique arementioned in detail in the following references.

[0049] Japanese Patent Application No. 10-104652 (priority applicationof Japanese Patent Application No. 9-124493) discloses a technique forturning a memory cell in an over-erase state to a normal state by softwrite (as well as for making erase verification).

[0050] Japanese Patent Application No. 9-340971 discloses a techniquefor conducting soft write and erase verification after erasing data froman NAND cell, determining that there are predetermined number of memorycells which threshold voltages reach a predetermined threshold voltageto finish the soft write and turning memory cells in an over-erase stateinto a normal state.

[0051] Japanese Patent Application No. 9-224922 discloses a techniquefor conducting erase verification and over-erase detection read whileerasing data from an NAND cell and conducting data erase and soft writeso that the threshold voltages in an erase state can be set between adesired upper limit and a desired lower limit while monitoring thethreshold voltages of the memory cells.

[0052]FIGS. 4A and 4B show the concept of the soft write technique.

[0053] As indicated by “INITIAL” in solid line in FIG. 4B, thedistribution of threshold voltages Vth after block erase or batch eraseis very wide.

[0054] As indicated by “Tb” which is gradient shown in FIG. 4A, however,a memory cell easy to erase is also easy to write.

[0055] Accordingly, by optimizing a voltage for block erase or batcherase, a start voltage for later soft write as well as a step-up widthto conduct erase verification for each block, it is possible to narrowthe distribution width of threshold voltages Vth after data erase asindicated by “SOFTW” in dotted line shown in FIG. 4B. The reason forconducting verification for each block is that it requires shorter timeto complete verification than the time required for conductingverification for each bit. As a result, it is possible to narrow thedistribution width of the threshold voltages Vth compared with thatafter block erase or batch erase. Naturally, however, the distributionwidth narrowed by the soft write is greatly influenced by theirregularity of the write characteristic of memory cells within therespective blocks. For that reason, there is fear that the followingproblems may occur to the controlling of the distribution width by meansof the soft write technique as miniaturization progresses in the future.

[0056]FIG. 5A shows the dependency of write characteristic on gatelength. It is noted that the dependency is obtained under constantconditions for a voltage applied during data write and for a write pulsewidth.

[0057] As shown in FIG. 5A, the dependency of write characteristic ongate length is particularly great when a gate length L is within therange of 0.25 μm or less. This is due to the influence of processirregularity, the short channel effect and the like. The greatdependency of write characteristic on gate length means that writecharacteristic varies according to wafers, chips and blocks as the gatelength L is shorter. It is not favorable to conduct verification at thetime of soft write for each bit due to the limited erase time.Verification is, therefore, conducted on a block-by-block basis.

[0058] Thus, the irregularity of write characteristic has greatinfluence on the distribution of threshold voltages after soft write.Consequently, writing errors and the variation of the threshold voltageincrease particularly in a memory cell having a gate length L decreasedto not more than 0.25 μm.

[0059] As can be seen from the above, the LSB technique is a promisingtechnique among NAND cell write techniques, for preventing writing erroror threshold voltage variation which may occur during write operation.

[0060] Nevertheless, as the miniaturization of memory cells progresses,it becomes more difficult to control the distribution of thresholdvoltages after data erase. Such controlling is quite significant for theLSB technique. If the distribution width of threshold voltages afterdata erase increases, writing errors or the like occur to the writeoperation after erase operation, resulting in the deterioration ofreliability.

BRIEF SUMMARY OF THE INVENTION

[0061] The present invention has been made in view of the abovecircumstances. The main object of the present invention is to provide anonvolatile semiconductor memory capable of preventing the increase ofthe distribution width of threshold voltages after data erase even ifthe miniaturization of memory cells progresses.

[0062] Another object of the present invention is to provide anonvolatile semiconductor memory capable of shortening time required forreading multilevel data.

[0063] In order to attain the above main object, there is provided anonvolatile semiconductor memory device comprising: a memory sectionincluding at least one variable threshold voltage type memory cell, thevariable threshold voltage type memory cell storing data according to athreshold voltage of the memory cell; and a signal line which transmitsa potential related to data stored by the variable threshold voltagetype memory cell, wherein during a data stored in the memory cell iserased, a soft erase operation to gradually shifted the thresholdvoltage of the memory cell in one of a negative direction or a positivedirection is carried out.

[0064] According to the above invention, the threshold voltage of thenonvolatile memory cell is gradually moved in the negative direction andthen data is erased from the nonvolatile memory cell.

[0065] With such an erase technique, the dependency of, for example, thenonvolatile memory cell on gate length is small, compared with aconventional soft write technique for gradually moving the thresholdvoltage of a nonvolatile memory cell in positive direction and narrowingthe distribution width of the threshold value after data erase.

[0066] Thus, even if the miniaturization of a memory cell progresses, itis possible to suppress the increase of the distribution width of thethreshold value after data erase. As a result, it is possible tosuppress the occurrence of writing errors and threshold voltagevariation during data write operation carried out after the data erase.The suppression of the threshold voltage variation contributes to thestabilization of data particularly in a multilevel storage memory.

[0067] Moreover, since the increase of the distribution width of thethreshold value after the data erase can be suppressed, it is possibleto effectively utilize the local self boost technique for data write.

[0068] In order to attain the above another object, there is provided anonvolatile semiconductor device comprising: a memory cell arrayincluding at least first and second memory cells each storing n-leveldata, where n is an integer not less than 4; a first wiring whichapplies a source potential to the first memory cell; and a second wiringwhich applies a source potential to the second memory cell, wherein whendetermining the n-level data, read of the n-level data is divided intonot less than m and less than (n−1) data read operations, where m is alowest integer satisfying log₂n≦m; among the divided data readoperations, a first data read operation is carried out while setting thesource potentials of the first and second memory cells at a commonpotential; and a second data read operation following the first dataread operation is carried out according to a result of the first dataread operation while individually setting the source potentials of thefirst and second memory cells.

[0069] According to the above invention, the second data read followingthe first data read is carried out while individually setting the sourcepotentials of the first and second memory cells in accordance with theresult of the first data read. By individually setting the sourcepotentials during the second data read, the threshold voltages of thememory cells are shifted according to the result of the first data read.As a result of shifting the threshold voltages, it is possible to applya common potential to the gates of the memory cells in the second dataread.

[0070] Needless to say, by individually setting the source potentials ofthe first and second memory cells according to the result of theprevious data read as in the case of the above, it is possible to applya common potential to the gates of the memory cells in data readfollowing the second data read.

[0071] Hence, the number of times of data read can be reduced comparedwith the conventional one and time required for reading multilevel datacan be shortened.

[0072] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0073] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0074]FIG. 1A is a plan view of an NAND cell;

[0075]FIG. 1B is an equivalent circuit of the NAND cell;

[0076]FIG. 2A is a cross-sectional view taken along the line 2A-2A ofFIG. 1A;

[0077]FIG. 2B is a cross-sectional view taken along the line 2B-2B ofFIG. 1A;

[0078]FIG. 3 is a cross-sectional view taken along the line 2B-2B ofFIG. 1A and showing another example;

[0079]FIGS. 4A and 4B show the concept of a soft write technique,respectively;

[0080]FIG. 5A is a graph showing the dependency of write characteristicon gate length;

[0081]FIG. 5B is a graph showing the dependency of erase characteristicon gate length;

[0082]FIG. 6 is a flowchart showing data erase operation in the firstembodiment according to the present invention;

[0083]FIG. 7 shows the concept of a soft write technique according tothe present invention;

[0084]FIG. 8 is a circuit diagram of a memory cell array;

[0085]FIGS. 9A, 9B, 9C and 9D are graphs showing threshold voltagedistributions, respectively;

[0086]FIG. 10 is a circuit diagram showing two NAND cells;

[0087]FIG. 11 is a graph showing the relationship between the thresholdvoltages of adjacent cells and a voltage Vpass;

[0088]FIG. 12 is a flowchart showing data erase operation in the secondembodiment according to the present invention;

[0089]FIGS. 13A and 13B are graphs showing threshold voltagedistributions, respectively;

[0090]FIG. 14A shows an example of a Vpwell pulse during soft erase;

[0091]FIG. 14B shows an example of a voltage at each terminal duringsoft erase;

[0092]FIG. 15A shows an example of a Vpwell pulse during soft write;

[0093]FIG. 15B shows an example of a voltage at each terminal duringsoft write;

[0094]FIG. 16 is a graph showing the distribution of threshold voltagesof memory cells having the data level number of “4”;

[0095]FIG. 17 is a block diagram of a four-level data storage NAND typeEEPROM;

[0096]FIG. 18A is a graph showing the distribution of threshold voltagesof memory cells having the data level number of “4”;

[0097]FIG. 18B is a graph showing the distribution of threshold voltagesof memory cells having the data level number of “8”;

[0098]FIG. 19A is a flowchart showing an ordinary four-level datareading method while the number of data levels is “4”;

[0099]FIG. 19B is a flowchart showing an ordinary eight-level datareading method while the number of data levels is “8”;

[0100]FIG. 20A is a flowchart showing a four-level data reading methodin the third embodiment according to the present invention;

[0101]FIG. 20B is a flowchart showing an ordinary four-level datareading method;

[0102]FIG. 20C is a graph showing the distribution of thresholdvoltages;

[0103]FIG. 21A shows two-bit data;

[0104]FIG. 21B shows three-bit data;

[0105]FIGS. 22A and 22B are explanatory views for set values of apositive potential Vm, respectively;

[0106]FIG. 23 is a block diagram showing an NAND type EEPROM to which afour-level data reading method in the third embodiment according to thepresent invention is applied;

[0107]FIG. 24 is a circuit diagram for a data determination circuitshown in FIG. 23;

[0108]FIG. 25 is a waveform view showing the operation of the NAND typeEEPROM shown in FIG. 23;

[0109]FIG. 26A shows the state of threshold voltages at the time ofreading bit data 1;

[0110]FIG. 26B shows the state of threshold voltages at the time ofreading bit data 2;

[0111]FIG. 27A is a flowchart showing an eight-level data reading methodin the fourth embodiment according to the present invention;

[0112]FIG. 27B is a flowchart showing an ordinary eight-level datareading method;

[0113]FIG. 27C is a graph showing the distribution of thresholdvoltages;

[0114]FIG. 28A is an explanatory view for the set values of a positivepotential Vm1;

[0115]FIG. 28B is an explanatory view for the set values of a positivepotential Vm2;

[0116]FIG. 29 is a block diagram showing an NAND type EEPROM to which aneight-level data reading method in the fourth embodiment according tothe present invention is applied;

[0117]FIG. 30 is a circuit diagram for a data determination circuitshown in FIG. 29;

[0118]FIG. 31 is a waveform view showing the operation of the NAND typeEEPROM shown in FIG. 29;

[0119]FIG. 32A shows the state of threshold voltages at the time ofreading bit data 1;

[0120]FIG. 32B shows the state of threshold voltages at the time ofreading bit data 2;

[0121]FIG. 32C shows the state of threshold voltages at the time ofreading bit data 3;

[0122]FIG. 33 is a flowchart showing a four-level data reading method inthe fifth embodiment according to the present invention;

[0123]FIG. 34 is a block diagram showing an NAND type EEPROM to which afour-level data reading method in the fifth embodiment according to thepresent invention is applied;

[0124]FIG. 35 is a circuit diagram showing a data determination circuitshown in FIG. 34;

[0125]FIG. 36 is a waveform view showing the operation of the NAND typeEEPROM shown in FIG. 34;

[0126]FIG. 37 is a flowchart showing an eight-level data reading methodin the sixth embodiment according to the present invention;

[0127]FIG. 38 is a block diagram showing an NAND type EEPROM to which aneight-level data reading method in the sixth embodiment according to thepresent invention is applied;

[0128]FIG. 39 is a circuit diagram showing a data determination circuitshown in FIG. 38;

[0129]FIG. 40 is a waveform view showing the operation of the NAND typeEEPROM shown in FIG. 38; and

[0130]FIG. 41 is a graph showing the relationship between the number ofdata levels and the number of times of data read.

DETAILED DESCRIPTION OF THE INVENTION

[0131] As already described above, it is important to set the erasethreshold voltage distribution to be put on a higher side within a rangein which a cell erase state is readable and to sufficiently narrow thedistribution width in case of the local self boost (LSB) technique.

[0132]FIG. 5B is a graph showing the dependency of erase characteristicon gate length. The dependency on the gate length shown therein isobtained under constant conditions for a voltage applied and an erasepulse width during data erase.

[0133] As shown in FIG. 5B, the dependency of erase characteristic ongate length is far smaller than that of write characteristic on gatelength shown in FIG. 5A. Owing to this, even if the gate length isreduced, the variation of threshold voltages due to erase operation canbe made small. The present invention utilizes the characteristics.

[0134] (First Embodiment)

[0135]FIG. 6 is a flowchart showing the data erase operation of an NANDtype EEPROM in the first embodiment according to the present invention.

[0136] In this embodiment, as shown in FIG. 6, when the distribution ofthreshold voltages of memory cells to be turned into an erase state iscontrolled, batch write operation is carried out first to each block ina memory cell array to be erased as shown in a step S11 (prewriteoperation).

[0137] Thereafter, as shown in a step 12, using a predetermined voltageas a start voltage, soft erase is carried out to each block.

[0138] Next, as shown in a step S13, erase verification read is carriedout. In a step S14, the threshold voltages of cells are compared with adetermination reference value.

[0139] As a result of the comparison in the step S14, if the thresholdvoltages of the cells do not reach the determination reference value(“NO” in the step S14), soft erase is repeated (in a loop S15). Thepredetermined voltage in the repeated soft erase is changed to a valuedifferent from the start voltage.

[0140] As a result of the comparison in the step S14, if all thethreshold voltages of the cells reach the determination reference value(“YES” in the step S14), soft write is finished here.

[0141] The control including the operation for converging the thresholdvalues of the cells after data erase is referred to as a soft erasetechnique. This soft erase technique indicates particularly useful dataerase working with the LSB technique to erase verification in the unitsof blocks. It originally differs from conventional erase operation.

[0142]FIG. 7 shows the concept of the soft erase technique.

[0143] As shown therein, there is a difference ΔVth between thethreshold voltage of a cell in which data is erased at the fastest speedand that of a cell in which data is erased at the lowest speed at thetime of data write in the step S11 of FIG. 6. The difference ΔVth isregarded as the distribution width of threshold voltages and controlledto be closer to a point at which the distribution width becomes thenarrowest as a result of soft erase, as will be described in detailbelow.

[0144]FIG. 8 is a circuit diagram showing an example of theconfiguration of a memory cell array on which NAND cells serving asmemory cell units (memory cell sections) are arranged in a matrix. WhileFIG. 8 shows a case where eight memory cells MC are connected in seriesto thereby construct an NAND cell, the NAND cell may be constructed byconnecting in series 4, 16 or 32 memory cells. The number of memorycells in an NAND cell should not be limited to any specific number.

[0145] Control gates (word lines WL (WL1 to WL8)) of memory cells MC,drain-side select gate lines SGD and source-side select gate lines SGSare arranged in row direction. Normally, a group of the memory cells MCconnected to one control gate is referred to as “one page” and a groupof pages put between a set of a drain-side select gate line SGD and asource-side select gate line SGS is referred to as “one NAND block” or“one block”.

[0146] “One page” consists of, for example, 256-byte (256×8) memorycells MC. Data are written to the memory cells MC included in “oneblock” almost simultaneously.

[0147] “One block” consists of, for example, 2048-byte (2048×8) memorycells MC. Data are erased from the memory cells MC included in “onepage” almost simultaneously.

[0148]FIGS. 9A to 9D are explanatory views sequentially showing the softerase technique of the present invention conducted for the NAND cellsshown in FIG. 8 and particularly show the variation of the thresholdvoltage distributions.

[0149] As shown in FIG. 9A, a predetermined high voltage Vpp, e.g. of20V is applied to word lines WL1 to WL8 connected to all of the bits ina block in which data are erased (see FIG. 8), and data write is carriedout (which operation corresponds to the-step S11 shown in FIG. 6). Bydoing so, the threshold voltages of all of the memory cells MC in theerase target block are moved in positive direction. At the time ofcarrying out this data write, the voltages of the respective bit linesBL are 0V, that of the bit-side select gate line SGD is a predeterminedpositive voltage Vsgd, that of a source line SL is 0V or Vs which is apositive voltage, and the source-side select gate line SGS is 0V.

[0150] The write voltage Vpp should not be limited to 20V and may beselected so that all of the bits in the block may have sufficiently highthreshold voltages (e.g., preferably about 1.5V, which voltages largelydepend on erase speed, the neutral threshold voltage of memory cells andthe like and need to be optimized).

[0151] Next, as shown in FIG. 9B, 0V or a sufficiently low voltage,positive or negative, is applied to all of the word lines WL1 to WL8 inthe data erase target block, a start voltage of Vpp, e.g., 12V, isapplied to a well and data erase is carried out (which operationcorresponds to the step S12 shown in FIG. 6). At this moment, word linesin blocks in which data erase is not carried out are applied with avoltage, for example, the same voltage as that of the well, to preventdata erase.

[0152] Next, an erase state is read for each block (which operationcorresponds to the step S13 shown in FIG. 6).

[0153] To do so, all the word lines WL1 to WL8 in the block are appliedwith, for example, 0V and a positive voltage is applied from the sourceline SL to the channels of the memory cells in this block.

[0154] At this time, if the memory cell having the highest thresholdvoltage is still in a write state among the memory cells MC in theblock, the potentials of the bit lines do not increase sufficiently.Consequently, it is judged that soft erase has not been carried outenough (which judgment corresponds to the step S14 shown in FIG. 6). Ifso judged, as shown in FIG. 9C, soft erase is carried out once again(which operation corresponds to the loop S15 shown in FIG. 6). The erasevoltage of the second erase differs from the above-stated start voltageand is set at, for example, 12.2V higher than the start voltage by 0.2V(with a step voltage of 0.2V).

[0155] The above start voltage Vpp or step voltage is selected so thatthe threshold voltage distribution width after soft erase becomes thenarrowest and that soft erase time is the shortest and, therefore,should not be limited to the above values. Specifically, they are set atoptimum values in light of the neutral threshold value of memory cells,a coupling ratio which determines write/erase characteristics and thelike.

[0156] Thereafter, memory cell verification is read for each block as inthe case of the above. If the memory cell having the highest thresholdvoltage in the block does not reach a certain determination referencevalue, soft erase is further carried out with the voltage Vpp stepped upby, for example, 0.2V repeatedly (which operation corresponds to theloop S15 shown in FIG. 6).

[0157] Here, assuming that the threshold voltage by which the end ofsoft erase is determined is, for example, −0.5V, the bit lines BL areapplied with a potential of 0.5V from the source line SL in the step S13shown in FIG. 6. Following this, by monitoring whether the potentials ofthe bit lines BL are not less than 0.5V or not more than 0.5V,verification operation after data erase may be carried out. Namely, ifthe memory cell having the highest threshold voltage reaches a desiredthreshold voltage (determination reference voltage), the potentials ofthe bit lines sufficiently rise to not less than 0.5V and the end ofsoft erase is determined (FIG. 9D).

[0158] In the above-stated first embodiment, the desired distributionwidth of threshold voltages after data erase is such that the highestthreshold voltage is above −0.5V and the lowest threshold voltage isabout −2.5V. The narrower the distribution width, the better.

[0159] The reason for setting the desired distribution width between−0.5 to −2.5V lies in the fact that the threshold voltage distributionwidth is preferably 2V or less. Thus, the distribution width should notbe limited to the range between −0.5V and −2.5V.

[0160] In addition, in the first embodiment, an example of controllingof erase verification read operation is described. The control techniqueshould not be limited to that described in the first embodiment. Anytechnique which allows reading negative threshold voltages for eachblock may be employed.

[0161] Furthermore, in the first embodiment, it is detected that thehigher threshold voltage of those after erase is not more than a desiredupper limit. It is also possible to detect that the lower thresholdvoltage of the threshold voltages after erase is not less than a desiredlower limit.

[0162] Conventionally, soft write controls the distribution width ofthreshold voltages after erase so as to narrow it. The soft write is,like ordinary write operation, an operation for injecting electrons intoa floating gate. Due to this, as shown in FIG. 5A, the soft writelargely depends on the gate length. As a result, if the gate length isshortened particularly to 0.25 μm or less, the distribution width ofthreshold voltages after soft write in the block increases, making itdifficult to control threshold voltages so as to be suitable forminiaturization.

[0163] In the first embodiment, by contrast, soft erase controls thedistribution width of threshold voltages after erase so as to narrow it.The soft erase is, like ordinary erase operation, an operation fortaking out electrons from the floating gate and has, therefore, smalldependency on the gate length as shown in FIG. 5B. Do to this, comparedwith the conventional soft write, the soft erase technique in the firstembodiment is quite effective for miniaturization in the future. Thesoft erase can suppress, in particular, the distribution width ofthreshold voltages to be sufficiently narrow even if the gate length isshortened to 0.25 μm or less.

[0164] Further, since it is possible to control threshold voltages aftererase with high accuracy, the soft erase technique in the firstembodiment is quite effective for multilevel data memories required toseparate threshold voltage into a plurality of voltages.

[0165] By employing the soft erase technique stated above, it ispossible to make the threshold voltage distribution after data erasevery narrow and to realize memory cells having the far smaller variationof threshold voltages and far less chances of writing errors in thelater write operation.

[0166] Data are written to the cells by using the soft erase right afternarrowing the threshold voltage distribution after data erase. This datawrite operation is preferably carried out by means of the LSB techniquedescribed in “Prior Art” section.

[0167]FIG. 10 is a circuit diagram showing two NAND cell units pickedout from FIG. 8. FIG. 10 also shows the relationship among the voltagesof the respective terminals in regard of data write employing the LSBtechnique.

[0168] (Data Write Operation (LSB Technique))

[0169] Before starting the description of the data write operation, itis assumed that a select word line WL (control gate) in a select blockis “WL2” shown in FIG. 10.

[0170] In the data write, a predetermined positive voltage Vsgd isapplied to a select gate line SGD in the select block and a voltage of0V (Vss) is applied to the select gate line SGS. A voltage of 0V (Vss)is applied to all of the word lines WL in the non-select blocks and allof the select gate lines SGD and SGS in the non-select blocks.

[0171] In the data write by means of the LSB technique in this state, ahigh voltage Vpp for data write is applied to the select word line WL2,a voltage of 0V (Vss) is applied to the non-select word lines WL1 andWL3 adjacent to the select word line WL2, and a voltage Vpass is appliedto non-select word lines WL4 to WL8 other than the non-select word linesWL1 and WL3. The voltage Vpass is almost in the middle of 0V (Vss) andthe high voltage Vpp for data write. The high voltage Vpp may be, forexample, 18V and the voltage Vpass may be, for example, 9V. Although 0Vis applied to the non-select word lines WL1 and WL3, a positive voltagelower than the voltage Vpass may be applied thereto.

[0172] Normally, data write is sequentially carried out from memorycells MC18 and MC28 farthest from the bit lines BL toward memory cellsMC11 or MC21 closest to the bit lines BL.

[0173] If data “0” (which is data having a “positive” threshold voltagein this example) is written to, for example, the memory cell MC12, 0V(write select voltage) is applied to the select bit line BL(E). The dataof the memory cell MC11 existing at the bit line BL side with respect tothe select memory cell MC12 is always in an erase state (which is datahaving a “negative” threshold voltage in this example). Owing to this,even if the voltage of the word line WL1 is set at 0V, the voltage of 0Vapplied to the bit line BL is transferred up to the channel of and theN⁺ type diffused layer of the select memory cell MC12. As a result, inthe select memory cell MC12, electrons are moved from the P type well tothe floating gate thereof and the threshold voltage of the select memorycell MC12 is shifted in positive direction.

[0174] If data “1” (which data has a “negative” threshold voltage) iswritten to the memory cell M22 simultaneously, a voltage Vb1 (writenon-select voltage) is applied to the select bit line BL(O). The voltageVb1 is normally set at a positive voltage equal to or higher than thevoltage Vsgd.

[0175] At this moment, the voltage of the drain-side select gate lineSGD is Vsgd, so that a select gate transistor ST1 becomes non-conductiveand the channels of the memory cells MC21 to MC28 and N⁺ type diffusedlayers thereof are turned into “a floating state”, respectively. Here,the high voltage Vpp is applied to the select word line WL2 and thevoltage Vpass is applied to the non-select word lines WL4 to WL8. Due tothis, the channel potential of the select memory cell MC22 and those ofthe non-select memory cells MC24 to MC28 as well as those of the N⁺ typediffused layers thereof increase.

[0176] Memory cells MC21 and MC23 adjacent to the select memory cellMC22 are cut off by means of the back-bias effect derived from theincreased channel potentials. At this moment, if the high voltage Vpphas been applied to the control gate of the select memory cell MC22,then the control gate of the memory cell MC22 is coupled with thechannel and N⁺ type diffused layer of the memory cell MC22 and thechannel potential of the memory cell MC22 increases.

[0177] This channel potential rises to about 8 to 9V if the high voltageVpp is 18V and a channel boost ratio is 0.5. That is, the differencebetween the potential of the word line WL2 and the channel potential ofthe select memory cell MC22 is decreased to a sufficient value toprovide a write prohibit voltage. As a result, in the select memory cellMC22, there is little movement of electrons from the P type well to thefloating gate and the threshold voltage of the select memory cell MC22is kept “negative”.

[0178] It is noted that the voltages of the word lines WL1 and WL3adjacent to the select word line WL2 are not necessarily 0V and may below enough to be capable of turning the memory cells in a cutoff state.

[0179] Furthermore, the voltage of the source-side word line WL3adjacent to the select word line WL2 may be negative.

[0180] It is also possible to apply a low voltage enough to be capableof turning the memory cells into a cutoff state, only to the source-sideword line WL3 out of the word lines WL1 and WL3 adjacent to the selectword line WL2 and to sequentially write data to arbitrary memory cellsin the NAND cells.

[0181] As the above-stated voltage Vpass is higher, the variation of thethreshold voltages of the memory cells connected to the word lineapplied with a high voltage (select word line) and to the bit linesapplied with the write non-select voltage Vb1, i.e., the memory cells towhich “1” data is written can be limited to be smaller.

[0182] However, since the variation of the threshold voltages of thememory cells connected to the word lines (non-select word lines) appliedwith the voltage Vpass and to the bit lines applied with the writeselect voltage 0V becomes greater, the voltage Vpass cannot be set sohigh.

[0183]FIG. 11 shows the relationship between the threshold voltages Vthof the memory cells MC21 and MC23 both in an erase state and the voltageVpass, and the relationship between the threshold voltage Vth of thememory cell MC22 and the voltage Vpass. It is noted that therelationships shown in FIG. 11 indicate the variation of thresholdvoltages at the time of wiring data “1” to the memory cell M22 while 0Vis being applied to the control gates of the memory cells MC21 and MC23,respectively.

[0184] As can be seen from FIG. 11, not to vary the threshold voltageswhen the voltage Vpass is, for example, 8V, it is necessary that thelowest threshold voltage among the possible threshold voltages Vth ofthe memory cells in the erase state is higher than about −2.5V.

[0185] It is also preferable that the highest threshold voltage amongthe possible threshold voltages of the memory cells in the erase stateis lower than, for example, −0.5V. This is intended to ensure a marginat the time of data read. From this viewpoint, the allowabledistribution width of threshold voltages is set at −2.5<Vth<−0.5V. Inthis way, it is necessary to set the distribution width of the thresholdvoltages to be smaller than about 2V.

[0186] Furthermore, as the distribution width of the threshold voltagesof the memory cells in the erase state can be set narrower, the highestthreshold voltage can be further made low such as −1V. In this way, ifthe highest threshold voltage can be made low further, a read marginextends and the reliability of a nonvolatile semiconductor memoryenhances.

[0187] (Second Embodiment)

[0188]FIG. 12 is a flowchart showing the data erase operation of an NANDtype EEPROM in the second embodiment according to the present invention.

[0189] In this embodiment, to further narrow the distribution width ofthreshold voltages after data erase, soft write is carried out aftersoft erase. By doing so, it is possible to realize an NAND typenonvolatile semiconductor memory by means of the LSB technique with theless chances of writing errors.

[0190] Namely, as shown in FIG. 12, when the distribution of thethreshold voltages of memory cells to be turned into an erase state iscontrolled, data write is first carried out for each block as shown in astep S21.

[0191] Thereafter, as shown in a step S22, using a predetermined voltageas a start voltage, soft erase is carried out for each block.

[0192] Next, verification read is executed in a step S23 and then thethreshold voltages of the cells are compared with a determinationreference voltage as shown in a step S24.

[0193] As a result of the comparison in the step S24, if the thresholdvoltages of the cells do not reach the determination reference value(“NO” in the step S24), soft erase is repeated (in a loop S25). Thepredetermined voltage of the soft erase is changed from the startvoltage. When the threshold voltages of all the cells reach thedetermination reference value (or, in this embodiment, when the highererase threshold voltage decreases and reaches the determinationreference value), the soft erase is finished.

[0194] Thereafter, as shown in steps S26 to S29, the soft write and theverification read are repeated and the lower erase threshold voltage aremade higher and higher. That is to say, after the verification read inthe step S27, the higher threshold voltage of the cell is compared withthe determination reference value as shown in the step S28. Then, if thehigher threshold voltage of the cell does not reach the determinationreference value, soft write is repeated (in the loop S29). Thepredetermined voltage in the soft write is changed from the startvoltage. When the threshold voltage of at least one cell reaches thedetermination reference value (or, in this embodiment, when the highererase threshold voltage grows higher and reaches the determinationreference value), the soft write operation is finished.

[0195]FIGS. 13A and 13B are graphs showing the distributions of erasethreshold voltages for describing the above-stated operation example,respectively. First, a determination reference value for soft write isset at, for example, −0.8V. The soft erase is then carried out (in stepsS22 to S25 in FIG. 12). When the highest threshold voltage of the memorycell in the erase threshold voltage distribution becomes lower than−0.8V, the soft erase is finished (FIG. 13A).

[0196] For the later soft write, a determination reference value is setat, for example, −0.5V. The soft write is then carried out (whichoperation corresponds to that in steps S26 to S29 in FIG. 12). When thehighest threshold voltage of the cell in the erase threshold voltagedistribution exceeds −0.5V, the soft write is finished (FIG. 13B).

[0197] In the above-stated verification reading method, a margin voltageof, for example, 0.3V is applied as a word line voltage. In this case,if a bit line potential of 0.8V is defined as a fixed determinationreference value, it is possible to determine whether or not thethreshold voltages of the memory cells are higher than −0.8V and notmore than −0.5V. In other words, it is possible to make a determinationof “FAILURE” when the threshold voltages are not more than −0.5V (seeJapanese Patent Application No. 9-340971).

[0198] These series of the soft erase and soft write are carried outonce or several times (in the loop S30 in dotted line shown in FIG. 12)while appropriately selecting the determination reference value, therebymaking it possible to provide a narrower distribution of thresholdvoltages after data erase than that in the first embodiment. The verynarrow distribution of threshold voltages after data erase thus providedallows data write at quite a low voltage Vpass (e.g., 7V). Consequently,it is possible to further prevent the occurrence of writing errors andto thereby realize highly reliable memory cells.

[0199]FIG. 14A is a waveform view showing an example of controlling thestart voltage and step-up voltage for soft write applied to the presentinvention. FIG. 14B is a circuit diagram showing one NAND cell in oneblock. In FIG. 14B, an example of a voltage applied during soft write bymeans of a step-up technique is shown.

[0200] A voltage Vpwell applied to the P type well is stepped up by 0.2Vwith a start voltage of, for example, 12V. Each application time is 15μsec. The voltage Vpwell finally applied to the well is controlled sothat it can be stepped up to 14V. Needless to say, if set conditions forerase threshold voltages are satisfied in a step-up stage before thevoltage Vpwell becomes 14V, the soft erase is finished. This control isapplicable to the soft erase operation in both the first and secondembodiments.

[0201]FIG. 15A is a waveform view showing an example of controlling astart voltage and a step voltage for soft write applied to the presentinvention. FIG. 15B is a circuit diagram showing one NAND cell in oneblock. In FIG. 15B, an example of a voltage applied during soft write bymeans of the step-up technique is shown.

[0202] It is assumed that a voltage Vpwell applied to the well is 0V. Avoltage Vpp applied to word lines (control gates) is stepped up by 0.2Vwith a start voltage of, for example, 12V. Each voltage application timeis 15 μsec. and a voltage finally applied to the word lines iscontrolled to be stepped up to 14V. Needless to say, if set conditionsfor erase threshold voltages are satisfied in a step-up stage before thevoltage becomes 14V, the soft write is finished. Such control isapplicable to the soft write operation in the second embodiment statedabove.

[0203] The start voltage and step voltage of the voltage Vpwell or thoseof the high voltage Vpp are selected so that the distribution width ofthreshold voltages after soft erase and soft write can become smallestand time for converging the erase threshold voltage can be shortest, andthey should not be limited to those described above. They may beappropriately determined in view of, for example, the neutral thresholdvoltage of the memory cells, a coupling ratio for determiningwrite/erase characteristics and the like.

[0204]FIG. 16 is a graph showing a threshold voltage distribution fordividing the storage data of memory cells in a four-level multilevelmemory in the first and second embodiments. In FIG. 16, data are dividedinto one data (“11”) at an erase side (at which threshold voltages arenegative) and three items of data (“10”, “01” and “00”) at a write side(at which threshold voltages are positive).

[0205] The way to divide three items of data having positive thresholdvoltages is described in, for example, Japanese Patent Application No.10-104652. For instance, time for applying a control voltage necessaryfor data write is set differently according to data.

[0206] That is to say, when writing data “10”, time for applying a writeselect voltage of 0V to bit lines is set shorter than that when wiringdata “01” and “00”. This is because the smaller amount of electrons maybe injected to floating gates of memory cells to store the data “10”than those injected to store data “01” and “00”.

[0207] Likewise, when writing data “01”, time for applying a writeselect voltage of 0V to bit lines is set shorter than that for wiringdata “00”. When writing the data “00”, time for applying a write selectvoltage of 0V to bit lines may be set longer than that for writing thedata “10” and “01”. For example, a write pulse length may be controlledso that time for applying a write select voltage of 0V to the bit linesfor writing the data “10”, “01” and “00” may be 1 μsec., 5 μsec. and 25μsec., respectively.

[0208] During data read, a read voltage Vread (e.g., 3.5V) is applied toa select gate line in a select block and word lines in non-select memorycells, respectively. By doing so, the non-select memory cells are turnedon. In this state, a predetermined read voltage is applied to the wordline of the select memory cell. The predetermined voltage value isselected so that the select memory cell can be turned into either “aconductive state” or “a non-conductive state” according to the state ofthe threshold voltage of the select memory cell. By applying such apredetermined voltage to the control gate of the select memory cell, theselect memory cell is turned into either “a conductive state” or “anon-conductive state” according to the state of the threshold voltage ofthe select memory cell. As a result, a current flowing through the bitlines varies according to whether the select memory cell is in “aconductive state” or “a non-conductive state” and the potentials of thebit lines vary accordingly. By detecting the varied bit line potentials,one of a plurality of types of data is determined.

[0209] The soft erase technique of the present invention is employed toset the storage data of such a multilevel data memory. If so, it ispossible to greatly narrow the threshold voltage distribution at thetime of erasing data (or setting data “11”) and to thereby realizememory cells having the smaller variation of threshold voltages and lesschances of writing errors when writing the respective data.

[0210]FIG. 17 is a block diagram showing the configuration of afour-level data storage NAND type EEPROM (NAND flash memory) in thefirst or second embodiment stated above.

[0211] A bit line control circuit 2 for controlling bit lines and a wordline control circuit 6 are provided for a memory cell array 1 on whichmemory cells each including a plurality of bit lines, a plurality ofword lines and a common source line, and capable of electricallyrewriting data are arranged in a matrix.

[0212] The bit line control circuit 2 reads the data of a memory cell onthe memory cell array 1 through a bit line, detects the state of amemory cell on the memory cell array 1 through a bit line and applies awrite control voltage to a memory cell on the memory cell array 1through a bit line to thereby write data to the memory cell.

[0213] The bit line control circuit 2 includes a plurality of datastorage circuits for dividing four-level data (see Japanese PatentApplication No. 10-104652). The data of a memory cell selected by acolumn decoder 3 and read from the data storage circuit is outputoutside through a data input/output buffer 4 from a data input/outputterminal 5. The write data input to the output terminal 5 from outsideis input, as initial control data, to the data storage circuit selectedby the column decoder 3 through the data input/output buffer 4.

[0214] The word line control circuit 6 selects a word line on the memorycell array 1 and applies a voltage thereto necessary for data read,write or erase.

[0215] The memory cell array 1, the bit line control circuit 2, thecolumn decoder 3, the data input/output buffer 4 and the word linecontrol circuit 6 are controlled by a control signal and control voltagegeneration circuit 7. The control signal and control voltage generationcircuit 7 are controlled by a control signal input to a control signalinput terminal 8 from outside.

[0216] The control signal and control voltage generation circuit 7generates a voltage used in an algorithm shown in the flowchart ofeither FIG. 6 or 12 of the present invention. That is, to realize anerase state in which the distribution of threshold voltages of memorycells is very narrow, a write system voltage Vpp (variable) for blockwrite, normal write or soft write after soft erase, a well voltageVpwell (variable) for the soft erase to realize an erase state in whichthe distribution of threshold voltages of the memory cells is verynarrow, a read voltage Vread (variable) and the like are boosted,controlled and then generated by a power supply voltage of Vss (0V) toVcc (e.g., 3V).

[0217] According to the first and second embodiments stated above, it ispossible to set the erase threshold voltage distribution to be put athigher side (to thereby eliminate over-erase) and to make thedistribution sufficiently narrow within the range in which the erasestates of the EEPROM cells can be read.

[0218] As a result, in data write by means of the LSB technique, it ispossible to operate the EEPROM at smaller voltage Vpass and to greatlyreduce chances of memory cell writing errors or the variation ofthreshold voltages. Hence, the reliability of data write considerablyenhances compared with the conventional data write.

[0219] Further, according to the present invention, it is possible toexpect the realization of a nonvolatile semiconductor memory havingexcellent reliability capable of dealing with binary and multilevelmemories particularly miniaturized to not more than a 0.25 μm rule.

[0220] It is noted that the technique of the present invention forintroducing the block write to the soft erase is effective not only forthe LSB technique but also for various types of EEPROM's employing theself boost write technique.

[0221] Furthermore, the above-stated technique of the present inventionexerts its advantage without depending on memory cell structure, elementisolation structure (LOCOS, trench), the number of select gatetransistors, the types of data which can be stored in memory cells(multilevel data memory), production method and the like.

[0222] Additionally, the technique of the present invention forconverging a reference threshold voltage (threshold voltage after eraseoperation) is equally effective for a case where the distribution of thethreshold voltages of all data is at negative side or a case where onedata is stored among multilevel data greater than four-level data.

[0223] (Third Embodiment)

[0224] Conventionally, the number n of data levels stored in one memorycell has been “n=2”. In recent years, attention is paid to a multilevelmemory in which the number of data levels is set at “n≧3” as a techniquefor increasing a storage capacity.

[0225] If the number of data levels is assumed as, for example, “n=4”,two-bit data “00”, “01”, “10” and “11” can be stored in one memory. In aconventional memory having the number of data levels of “n=2”, twomemory cells are required to store two-bit data.

[0226] In such a multilevel memory having the number of data levels of“n=4”, even if the accumulation number of memory cells is the same asthat having the number of data levels of “n=2”, the storage capacity istwice as large as that of the latter memory. In this way, the multilevelmemory is a useful technique for increasing a storage capacity.

[0227] The theory for setting the number of data levels at “n≧3” is asfollows.

[0228] In memory cells of, for example, an EEPROM, the number of typesof the possible threshold voltages of the memory cells may be three ormore so as to set the number of data levels at “n≧3”.

[0229] To set the number of data levels at, for example, “n≧4”, thenumber of types of the possible threshold voltages of memory cells maybe four, i.e., “vth00”, “vth01”, “Vth10” and “Vth11”. To provide fourtypes of threshold voltages Vth, it suffices to divide the amount ofcharges stored in the floating gate of a memory cell into four stages.

[0230] Likewise, to set the number of data levels at “n≧8”, the numberof types of the possible threshold voltages of memory cells may beeight, i.e., “Vth000”, “Vth001”, “Vth010”, “Vth011”, “Vth100”, “Vth101”,“Vth110” and “Vth111”.

[0231] The multilevel EEPROM is required to repeat data read “data levelnumber n−1” times so as to determine a plurality of or not more thanthree threshold voltages and to convert them into multi-bit data.

[0232] To determine, for example, four types of threshold voltages,i.e., “Vth00”, “Vth01”, “Vth10” and “Vth11” and to convert them intotwo-bit data, i.e., “00”, “01”, “10” and “11”, respectively, it isnecessary to carry out the following data read three times as shown inFIG. 19A.

[0233] First Read:

[0234] Data read is carried out while setting the source potential of amemory cell at 0V and the gate potential thereof at a read voltagebetween “Vth11” and “Vth10”. If the memory cell is turned “on”(Vtc1>Vth), data “11” is determined. If the memory cell is turned “off”,one of the data “10”, “01” and “00” is determined.

[0235] Second Read:

[0236] Data read is carried while setting the source potential of thememory cell at 0V and the gate potential thereof at a read voltage Vtc2between “Vth10” and “Vth01”. If the memory cell is turned “on”(Vtc2>Vth), data “10” is determined. If the memory cell is turned “off”,either data “01” or “00” is determined.

[0237] Third Read:

[0238] Data read is carried out while setting the source potential ofthe memory cell at 0V and the gate potential thereof at a voltage Vtc3between “Vth01” and “Vth00”. If the memory cell is turned “on”(Vtc3>Vth), data “01” is determined. If the memory cell is turned “off”,data “00” is determined.

[0239] Likewise, to convert the eight types of the threshold voltages“Vth000”, . . . , “Vth111” into three-bit data of “000”, . . . , “111”respectively, it is necessary to carry out data read seven times asshown in FIG. 19B.

[0240] As can be seen from the above, the multilevel EEPROMadvantageously facilitates increasing storage capacity compared with theconventional EEPROM. However, it disadvantageously increase timerequired for data read.

[0241] Taking the above disadvantage into consideration, the thirdembodiment is designed to reduce time required for data read of anonvolatile semiconductor memory comprising memory cells each storingn-value data (where n is an integer not less than 4).

[0242] Now, the third embodiment of the present invention will bedescribed with reference to the drawings.

[0243] Before starting the description of the third embodiment, it isdefined herein that data of two bits or more are bit data 1, bit data 2,. . . , in the order of starting at data of the most significant bit. Tobe specific, as for two-bit data, it is defined that data of the mostsignificant bit is bit data 1, data of the least significant bit is bitdata 2 (see FIG. 21A). Likewise, it is defined that data of three bitsare bit data 1 which is the most significant bit data, bit data 2 andbit data 3 which is the least significant bit data (see FIG. 21B).

[0244]FIG. 20A is a flowchart showing a four-level data reading methodin the third embodiment according to the present invention. FIG. 20B isa flowchart showing an ordinary four-level data reading method. FIG. 20Cis a distribution view showing the distribution of threshold voltages ofmemory cells storing four-level data.

[0245] First, description will be given to the distribution of thresholdvoltages Vth of memory cells storing four-level data.

[0246] As shown in FIG. 20C, the distribution of threshold voltages Vthof memory cells storing four-level data is divided into four stages,which will be described in the ascending order as follows:

[0247] First stage: distribution at the peak of a threshold voltageVth11;

[0248] Second stage: distribution at the peak of a threshold voltageVth10;

[0249] Third stage: distribution at the peak of a threshold voltageVth01; and

[0250] Fourth stage: distribution at the peak of a threshold voltageVth00.

[0251] These four stages of the distribution of threshold voltages Vthcorrespond to two-bit data “11”, “00”, “01” and “00”, respectively.

[0252] The first stage is the distribution having the lowest thresholdvoltage Vth and corresponds to a data erase state (in which the amountof electrons at floating gates is smallest) of an ordinary flash memory.The second to fourth stages correspond to data write states and theamount of electrons injected to the floating gates increases in thisorder.

[0253] Conventionally, memory cell data having four stages of athreshold voltage distribution are converted into two-bit data byreading data “three” times as indicated in FIG. 20B. As for FIG. 20B,reference is made to the description given with reference to FIG. 19A.

[0254] In the four-level data reading method in the third embodiment, bycontrast, memory cell data having four stages of a threshold voltagedistribution can be converted into two-bit data by reading data “twice”as indicated in FIG. 20A. Description will be given hereinafter withreference to FIG. 20A.

[0255] First Read:

[0256] Data read is carried out while setting the source potential Vs ofa memory cell at 0V and the gate potential thereof at a voltage Vtc2between “Vth10” and “Vth01”. If the memory cell is turned “on”(Vtc2>Vth), data is either data “11” or “10”. That is, it is determinedthat one of the two-bit data or bit data 1 in the third embodiment is“11”. If the memory cell is turned “off”, the data is either data “01”or “00”. That is, it is determined that bit data 1 is “0”.

[0257] Second Read:

[0258] Prior to carrying out the second read, the source potential Vs ofthe memory cell is changed based on the result of the first read. Thatis, if the bit data 1 is “1”, the source potential is changed from “0V”to a positive potential Vm. The level of the positive potential Vm isset at the following value so as to realize data read according to thepresent invention.

[0259]FIGS. 22A and 22B are explanatory views for the setting of thepositive potential Vm.

[0260] As shown in FIG. 22A, if the source potential Vs of the memorycell is set at “0V”, the memory cell having a threshold voltage Vth of“Vtc1” is considered. The memory cell is basically MOSFET. Due to this,if the source potential Vs is a positive potential higher than “0V”, thethreshold voltage Vth is shifted in positive direction by the substratebias effect as in the case of an ordinary MOSFET.

[0261] Utilizing this phenomenon, the positive potential Vm is set sothat the threshold voltage Vth is shifted from “Vtc1” at which thesource potential is “0V”, to “Vtc3”, as shown in FIG. 22B.

[0262] In this way, the value of the positive potential Vm is determinedand the source potential Vs is individually set for each memory cell.

[0263] It is noted that if the bit data 1 is “0”, the source potentialof the-memory cell substantially remains “0V”.

[0264] While the source potential Vs of the memory cell is setindividually and the gate potential thereof is set at a read voltageVtc3 between “Vth01” and “Vth00”, data read is carried out. If thememory cell is turned “on” (Vtc3>Vth), the data is either “01” or “11”.That is, it is determined that the other one of the two-bit data or bitdata 2 in the third embodiment is “1”. If the memory cell is turned“off”, the data is either “00”, or “10”. That is, it is determined thatbit data 2 is “0”.

[0265] According to the above-stated third embodiment, the bit data 1 isdetermined in the first read and, if the bit data 1 is “1”, the sourcepotential Vs is changed from “0V” to “Vm”. It is thereby possible toshift the threshold voltage which has been “Vth11” when the sourcepotential is “0V”, to “Vth01”. At the same time, it is possible to shiftthe threshold voltage which has been “Vth10” when the source potentialis “0V”, to “Vth00”.

[0266] Thus, it is possible to determine the bit data 2 by carrying outthe second read operation in which the gate potential is set at Vtc3 forboth a group of data “01” and “00” and a group of data “11” and “10”.

[0267] Consequently, by carrying out data read twice, the four-leveldata stored in one memory cell can be converted to two-bit data.Compared with the conventional method which requires carrying out readoperation three times when determining the four-level data, the presentinvention can determine four-level data only by carrying out data readtwice.

[0268] If the above-stated items are described algebraically, “in thedetermination of n-level data, the n-level data can be determined bycarrying out data read not less than m times (where m is the lowestinteger satisfying log₂n≦m) and less than (n−1) times” in the firstembodiment.

[0269] As can be seen from the above, according to the four-level datareading method in the third embodiment, the number of times of data readcan be reduced and time required for data read can be, therefore,shortened.

[0270]FIG. 23 is a block diagram showing an example of the configurationof an NAND type EEPROM to which the four-level data reading method inthe third embodiment is applied.

[0271] As shown in FIG. 23, the NAND type EEPROM has a memory cell array101, a row select circuit 102 selecting the row of the memory cell array101 and a data line circuit 103 reading data from the memory cell array101 and writing data to the memory cell array 101.

[0272] NAND cells 104 are formed on the memory cell array 101. Each ofthe NAND cells 104 includes memory cells MC1 to MC8 mutually connectedin series, a select transistor ST1 connected in series between thememory cell MC1 and a bit line BL (BLk, BLk+1) and a select transistorST2 connected in series between the memory cell MC8 and a source line SL(SLk, SLk+1).

[0273] The memory cells MC1 to MC8 are variable threshold voltage typeMOSFET's each having a floating gate FG for storing charge between thegate of the memory cell and the substrate thereof. The gates areconnected to word lines WL1 to WL8, respectively. The word lines WL1 toWL8 are connected to word line driving circuits 105-1 to 105-8 of therow select circuit 102, respectively. Each of the word line drivingcircuits 105-1 to 105-8 selects one word line WL for data read/writefrom among the word lines WL1 to WL8 according to a row address signalwhich is not shown in FIG. 23.

[0274] The select transistors ST1 and ST2 are ordinary MOSFET's and thegates of the transistors ST1 and ST2 are connected to select gate linesSG1 and SG2, respectively. The select gate lines SG1 and SG2 areconnected to the select gate line driving circuits 106-1 and 106-2 ofthe row select circuit 102, respectively. Each of the select gate linedriving circuits 106-1 and 106-2 selects one block (in FIG. 23, only oneblock is shown) for data read/write from the blocks put between theselect gate lines SG1 and SG2 according to a row address signal which isnot shown in FIG. 23.

[0275] The data line circuit 103 includes charge/ discharge circuits 107(107 k, 107 k+1), data determination circuits 108 (108 k, 108 k+1 ) fordetermining data to be read on the bit lines BL (BLk, BLk+1) and sourceline driving circuits 109 (109 k, 109 k+1) for driving source lines SL(SLk, SLK+1).

[0276]FIG. 24 is a circuit diagram for the data determination circuit108 k. While FIG. 24 shows the data determination circuit 108 k, thedata determination circuit 108 k+1 is similar to the circuit 108 k.

[0277] As shown in FIG. 24, the data determination circuit 108 k has asense amplifier/data latch circuit 101-1 for determining bit data 1 andlatching the determined bit data 1, a sense amplifier/data latch circuit110-2 for determining bit data 2 and latching the determined bit data 2,a connect/disconnect circuit 111-1 for connecting/disconnecting the bitline BLk and the sense amplifier/data latch circuit 110-1 in response toa connect/disconnect signal ø1, and a connect/disconnect circuit 111-2for connecting/ disconnecting the bit line BLk and the senseamplifier/data latch circuit 110-2 in response to ab connect/disconnectsignal ø2.

[0278] The sense amplifier/data latch circuit 110-1 has a positive-phasenode N1 and an anti-phase node /N1. The potential of the bit line BLk istransmitted to the positive-phase node Ni through the connect/disconnectcircuit 110-1. A reference potential Vref is transmitted to theanti-phase node /N1. The sense amplifier/data latch circuit 110-1compares and amplifies/latches the potential of the positive-phase nodeN1 and that of the anti-phase node /N1. The potentials of thepositive-phase node N1 and the anti-phase node /N1 thusamplified/latched are complementary signals indicating the bit data 1.

[0279] Likewise, the sense amplifier/data latch circuit 110-2 has apositive-phase node N2 and an anti-phase node /N2. The potential of thebit line BLk is transmitted to the positive-phase node N2 through theconnect/disconnect circuit 110-2. The above-stated reference potentialVref is transmitted to the anti-phase node /N2. The sense amplifier/datalatch circuit 110-2 compares and amplifies/latches the potential of thepositive-phase node N2 and that of the anti-phase node /N2. Thepotentials of the positive-phase node N2 and the anti-phase node /N2thus amplified/latched are complementary signals indicating the bit data2.

[0280] In this embodiment, after the bit data 1 is determined while thesource line SL (SLk, SLk+1) is set at 0V (Vss), the source line SL (SLk,SLk+1) is set at either 0V (Vss) or a positive potential Vm according tothe determination result of the bit data 1 and the bit data 2 is thendetermined. In the determination of the bit data 2, whether or not thepotential of the source line SL (SLk, SLk+1) is switched is determinedbased on the potential of the positive-phase node N1 (or anti-phase node/N1) of the sense amplifier/data latch circuit 110-1.

[0281] Next, the operation of the sense amplifier/data latch circuitwill be described. It is noted that the following description is givenwhile paying attention to the bit line BLk and assuming that the wordline WL3 is selected.

[0282]FIG. 25 is a waveform view showing the operation of the NAND typeEEPROM shown in FIG. 23. FIG. 26A shows the state of threshold voltagesat the time of reading bit data 1 and FIG. 26B shows the state ofthreshold voltages at the time of reading data bit 2.

[0283] As shown in FIG. 25, the bit line BLk is pre-charged with apotential Vpc at a time t0.

[0284] Next, at a time t1, signals ø1 and ø2 are temporarily set at “H”level and the positive-phase nodes N1 and N2 are pre-charged with thepotential Vpc.

[0285] At a time t2, while the potential of the source line SLK is setat 0V, the potentials of the select gate lines SG1 and SG2 are set at apotential Vread, that of the select word line WL3 is set at a potentialVtc2 and those of the non-select word lines WL1, WL2 and WL4 to WL8 atthe potential Vread. By doing so, the potential of the bit line BLk ischanged according to the threshold voltage of the memory cell MC3.

[0286] Namely, as shown in FIG. 26A, if the threshold voltage of thememory cell MC3 is higher than the potential Vtc2, the memory cell MC3is turned off and the potential of the bit line BLk substantiallyremains the potential Vpc. Also, if the threshold voltage of the memorycell MC3 is lower than the potential Vtc2, the memory cell MC3 is turnedon and the potential of the bit line BLk is lowered from the potentialVpc.

[0287] At a time t3, the signal ø1 is temporarily set at “H” level andthe potential of the bit line BLk is transferred to the positive-phasenode N1.

[0288] At a time t4, the potential of the positive-phase node N1 and thepotential Vref of the anti-phase node /N1 are compared/amplified. If thepotential of the positive-phase node Ni is higher than the potentialVref of the anti-phase node /N1, it is determined that the bit data 1 is“0”. If the potential of the positive-phase node N1 is lower, it isdetermined that the bit data 1 is “1”. In response to the determinationof the bit data 1 as “0” or “1”, the potential of the source line SLk ischanged. That is, when the bit data 1 is “0”, the potential of thesource line SLk remains 0V. When the bit data 1 is “1”, the potential ofthe source line SLk is set at the positive potential Vm.

[0289] In this embodiment, after the signal ø1 is changed from “H” levelto “L” level, all the potentials of the select gate lines SG1 and SG2,the select word line WL3 and the non-select word lines WL1, WL2 and WL4to WL8 are set at 0V.

[0290] Next, at a time t5, while the potential of the source line SLk isset at either 0V or the positive potential Vm, the potentials of theselect gate lines SG1 and SG2 are set at the potential Vread, that ofthe select word line WL3 is set at the potential Vtc3, those of thenon-select word lines WL1, WL2 and WL4 to WL8 are set at the potentialVread. By doing so, the potential of the bit line BLk is changedaccording to the threshold voltage of the memory cell MC3.

[0291] Namely, as shown in FIG. 26B, if the threshold voltage of thememory cell MC3 is higher than the potential Vtc3, the memory cell MC3is turned off and the potential of the bit line BLk substantiallyremains the potential Vpc. If the threshold voltage of the memory cellMC3 is lower than the potential Vtc, the memory cell MC3 is turned onand the potential of the bit line BLk is lowered from the potential Vpc.

[0292] At a time t6, the signal ø2 is temporarily set at “H” level andthe potential of the bit line BLk is transferred to the positive-phasenode N2.

[0293] At a time t7, the potential of the positive-phase node N2 and thepotential Vref of the anti-phase node /N2 are compared/amplified. If thepotential of the positive-phase node N2 is higher than the potentialVref of the anti-phase node /N2, it is, determined that bit data 2 is“0”. If the potential of the positive-phase node N1 is lower than thepotential Vref, it is determined that the bit data 2 is “1”.

[0294] As can be understood from the above, with the NAND type EEPROMshown in FIG. 23, the four-level data stored in one memory cell can beconverted to two-bit data.

[0295] (Fourth Embodiment)

[0296] Next, an example of applying the present invention to aneight-level EEPROM will be described as the fourth embodiment.

[0297]FIG. 27A is a flowchart showing an eight-level data reading methodin the fourth embodiment according to the present invention. FIG. 27B isa flowchart showing a conventional eight-level data reading method. FIG.27C is a graph showing the distribution of threshold voltages of memorycells storing the eight-level data.

[0298] As shown in FIG. 27C, in the memory cell storing eight-leveldata, the distribution of threshold voltages Vth is divided into eightstages, which will be described in the ascending order as follows:

[0299] First stage: distribution at the peak of a threshold voltageVth111;

[0300] Second stage: distribution at the peak of a threshold voltageVth110;

[0301] Third stage: distribution at the peak of a threshold voltageVth101;

[0302] Fourth stage: distribution at the peak of a threshold voltageVth100;

[0303] Fifth stage: distribution at the peak of a threshold voltageVth011;

[0304] Sixth stage: distribution at the peak of a threshold voltageVth010;

[0305] Seventh stage: distribution at the peak of a threshold voltageVth001; and

[0306] Eighth stage: distribution at the peak of a threshold voltageVth000.

[0307] The eight stages of the distribution of threshold voltages Vthcorrespond to three-bit data “111”, “110”, “101”, “100”, “011”, “010”,“001” and “000”, respectively.

[0308] The first stage is the distribution in which the thresholdvoltage becomes the lowest and corresponds to a data erase state (inwhich state the amount of electrons at the floating gate is smallest) inan ordinary flash memory. The second to eighth stages correspond to datawrite states, respectively and the amount of electrons injected to thefloating gate increases in this order.

[0309] Conventionally, the data of a memory cell having eight stages ofthe threshold voltage distribution is converted to three-bit data bycarrying out data read seven times as shown in FIG. 27B.

[0310] In the data reading method in the fourth embodiment, by contrast,the data of a memory cell having eight stages of the threshold voltagedistribution can be converted to three-bit data by carrying out dataread three times as shown in FIG. 27A, which will be describedhereinafter.

[0311] First Read:

[0312] While source potential Vs of the memory cell is set at 0V and thegate potential thereof is set at a read voltage Vtc4 between “Vth100”and “Vth011”, data read is carried out. If the memory cell is turned“on” (Vtc4>Vth), data is one of “111”, “110”, “101” and “100”. That is,it is determined that one of the three-bit data or bit data 1 in thefourth embodiment is “1”. If the memory cell is turned “off”, the datais one of “011”, “010”, “001” and “000”. That is, it is determined thatthe bit data 1 is “0”.

[0313] Second Read:

[0314] Prior to carrying out the second read, the source potential Vs ofthe memory cell is changed based on the result of the first read. Thatis, if the bit data 1 is “1”, the source potential is changed from “0V”to a positive potential Vm1. The level of the positive potential Vm1 isset at the following value.

[0315]FIG. 28A is an explanatory view for the setting of the value ofthe positive potential Vm1.

[0316] As shown in FIG. 28A, a memory cell having the threshold voltageVth of “Vtc2” when the source potential Vs is “0V”, is considered. Thepositive potential Vm1 is set so that the threshold voltage Vth of thememory cell is shifted from “Vtc2” to “Vtc6”.

[0317] The value of the positive potential Vm1 is determined as statedabove and the source potential Vs is individually set for each memorycell.

[0318] It is noted that if the bit data 1 is “0”, the source potentialremains “0V”.

[0319] While the source potential Vs is individually set and the gatepotential is set at a read voltage Vtc6, data read is carried out. Ifthe memory cell is turned “on” (Vtc6>Vth), data is one of “011”, “010”,“111” and “110”. That is, it is determined that the second data of thethree-bit data or bit data 2 in the fourth embodiment is “1”. If thememory cell is turned “off”, the data is one of “000”, “001”, “100” and“101”. That is, it is determined that the bit data 2 is “0”.

[0320] Third Read:

[0321] Prior to carrying out the third read, the source potential Vs ofthe memory cell is changed based on the result of the second read. Thatis, if the bit data 2 is “1”, a positive potential Vm2 is added to thesource potential Vs at the first read. The level of the positivepotential Vm2 is set at the following value.

[0322]FIG. 28B is an explanatory view for the setting of the value ofthe positive potential Vm2.

[0323] As shown in FIG. 28B, a memory cell having the threshold voltageVth of “Vtc5” when the source potential Vs is “0V” and “Vm”, isconsidered. The positive potential Vm2 is set so that the thresholdvoltage Vth of the memory cell is shifted from “Vtc5” to “Vtc7”.

[0324] The value of the positive potential Vm2 is determined as statedabove and the source potential Vs is individually set for each memorycell according to the bit data 2.

[0325] It is noted that if the bit data 2 is “0”, the source potentialremains “0V” or “Vm”.

[0326] While the source potential Vs is individually set and the gatepotential is set at a read potential Vtc7, data read is carried out. Ifthe memory cell is turned “on” (Vtc7>Vth), data is one of “001”, “011”,“101” and “111”. That is, it is determined that the third data of thethree-bit data or bit data 3 in the fourth embodiment is “1”. If thememory cell is turned “off”, the data is one of “000”, “010”, “100” and“110”. That is, it is determined that the bit data 3 is “0”.

[0327] Consequently, by carrying out data read three times, theeight-level data stored in one memory cell can be converted to three-bitdata. Compared with the conventional method which requires carrying outdata read seven times for determining eight-level data, therefore, themethod in this embodiment can determine the eight-level data by carryingout data read three times.

[0328]FIG. 29 is a block diagram showing an example of the configurationof an NAND type EEPROM to which the eight-level data reading method inthe fourth embodiment according to the present invention is applied. TheEEPROM shown in FIG. 29 differs from that shown in FIG. 23 in theconfiguration of a data line circuit 103′. To be specific, source linedriving circuits 109′ (109′k, 109′k+1) switch a source potential Vs toeither 0V (Vss) or a positive potential Vm1 according to the bit data 1and add a positive potential Vm2 to the source potential Vs according tothe bit data 2.

[0329]FIG. 30 is a circuit diagram for a data determination circuit108′k. While the data determination circuit 108′k is shown in FIG. 30, adata determination circuit 108′k+1 is similar to the circuit 108′k.

[0330] As shown in FIG. 30, the data determination circuit 108′k hassense amplifier/data latch circuits 110-1 to 110-3 andconnect/disconnect circuits 111-1 to 111-3. The connect/disconnectcircuits 111-1 to 111-3 connect/disconnect a bit line BLk and the senseamplifiers/data latch circuits 110-1 to 110-3 in response toconnect/disconnect signals ø1, ø2 and ø3, respectively.

[0331] The sense amplifier/data latch circuit 110-1 has a positive-phasenode N1 and an anti-phase node /N1. The potential of the bit line BLk istransmitted to the positive-phase node N1 through the connect/disconnectcircuit 111-1. A reference potential Vref is transmitted to theanti-phase node /N1. The sense amplifier/data latch circuit 110-1compares and amplifies/latches the potential of the positive-phase nodeN1 and that of the anti-phase node /N1. The potentials of thepositive-phase node N1 and the anti-phase node /N1 thusamplified/latched are complementary signals indicating bit data 1.

[0332] Likewise, the sense amplifier/data latch circuit 110-2 has apositive-phase node N2 and an anti-phase node /N2. The potential of thebit line BLk is transmitted to the positive-phase node N2 through theconnect/disconnect circuit 111-2. The above-stated reference potentialVref is transmitted to the anti-phase node /N2. The sense amplifier/datalatch circuit 110-2 compares and amplifies/latches the potential of thepositive-phase node N2 and that of the anti-phase node /N2. Thepotentials of the positive-phase node N2 and the anti-phase node /N2thus amplified/latched are complementary signals indicating bit data 2.

[0333] Likewise, the sense amplifier/data latch circuit 110-3 has apositive-phase node N3 and an anti-phase node /N3. The potential of thebit line BLk is transmitted to the positive-phase node N3 through theconnect/disconnect circuit 111-3. The above-stated reference potentialVref is transmitted to the anti-phase node /N3. The sense amplifier/datalatch circuit 110-3 compares and amplifies/latches the potential of thepositive-phase node N3 and that of the anti-phase node /N3. Thepotentials of the positive-phase node N3 and the anti-phase node /N3thus amplified/latched are complementary signals indicating bit data 3.

[0334] In this embodiment, while setting the source line SL (SLk, SLk+1)at 0V (Vss), the bit data 1 is determined and then the bit data 2 isdetermined by setting the source line SL (SLk, SLk+1) at either 0V (Vss)or the positive potential Vm1 according to the determination result ofthe bit data 1. Further, while setting the source line SL (SLk, SLk+1)at either 0V or the positive potential Vm1, the bit data 2 is determinedand then the bit data 3 is determined by adding the positive potentialVm2 to the potential of the source line SL (SLk, SLk+1) based on thedetermination result of the bit data 2.

[0335] In the determination of the bit data 2, whether or not thepotential of the source line SL (SLk, SLk+1) is switched is determinedbased on the potential of the positive-phase node N1 (or anti-phase node/N1) of the sense amplifier/data latch circuit 110-1.

[0336] In the determination of the bit data 3, whether or not thepositive potential Vm2 is added to the potential of the source line SL(SLk, SLk+1) is determined based on the potential of the positive-phasenode N2 (or anti-phase node /N2) of the sense amplifier/data latchcircuit 110-2.

[0337] Next, the operation of the sense amplifier/data latch circuit inthis embodiment will be described. It is noted that the followingdescription of the operation is given while paying attention to the bitline BLk and assuming that the word line WL3 is selected.

[0338]FIG. 31 is a waveform view showing the operation of the NAND typeEEPROM shown in FIG. 29. FIGS. 32A, 32B and 32C show threshold voltagestates at the time of reading bit data 1, bit data 2 and bit data 3,respectively.

[0339] As shown in FIG. 31, at a time t0, the bit line BLk ispre-charged with a potential Vpc.

[0340] At a time t1, the signals ø1, ø2 and ø3 are temporarily set at “Hlevel” and the positive-phase nodes N1, N2 and N3 are pre-charged withthe potential Vpc.

[0341] At a time t2, while setting the potential of the source SLk at0V, the potentials of the select gate lines SG1 and SG2 are set at apotential Vread, that of a select word line WL3 is set at a potentialVtc4 and those of non-select word lines WL1, WL2 and WL4 to WL8 are setat the potential Vread. By doing so, the potential of the bit line BLkis changed according to the threshold voltage of the memory cell MC3.

[0342] That is, as shown in FIG. 32A, if the threshold voltage of thememory cell MC3 is higher than the potential Vtc4, the memory cell MC3is turned off and the potential of the bit line BLk substantiallyremains the potential Vpc. If the threshold voltage of the memory cellMC3 is lower than the potential Vtc4, the memory cell MC3 is turned onand the potential of the bit line BLk is lowered than the potential Vpc.

[0343] At a time t3, the signal ø1 is temporarily set at “H level” andthe potential of the bit line BLk is transferred to the positive-phasenode N1.

[0344] At a time t4, the potential of the positive-phase node Ni and thepotential Vref of the anti-phase node /N1 are compared/amplified. If thepotential of the positive-phase node N1 is higher than the potentialVref of the anti-phase node /N1, it is determined that the bit data 1 is“0”. If the potential of the positive-phase node N1 is lower, it isdetermined that the bit data 1 is “1”. In response to the determinationof the bit data 1 as “0” or “1”, the potential of the source line SLk ischanged. That is, when the bit data 1 is “0”, the potential of thesource line SLk remains 0V. When the bit data 1 is “1”, the potential ofthe source line SLk is set at the positive potential Vm1.

[0345] Also, in this embodiment, after the signal ø1 is changed from “H”level to “L” level, all the potentials of the select gate lines SG1 andSG2, the select word line WL3 and the non-select word lines WL1, WL2 andWL4 to WL8 are set at 0V.

[0346] At a time t5, while setting the potential of the source line SLkat 0V or Vm1, the potentials of the select gate line SG1 and SG2 are setat the potential Vread, that of the select word line WL3 are set at apotential Vtc6 and those of the non-select word lines WL1, WL2 and WL4to WLB are set at the potential Vread. By doing so, the potential of thebit line BLk is changed according to the threshold voltage of the memorycell MC3.

[0347] That is, as shown in FIG. 32B, if the threshold voltage of thememory cell MC3 is higher than a potential Vtc6, the memory cell MC3 isturned off and the potential of the bit line BLk substantially remainsthe potential Vpc. If the threshold voltage of the memory cell MC3 islower than the potential Vtc6, the memory cell MC3 is turned on and thepotential of the bit line BLk is lowered from the potential Vpc.

[0348] At a time t6, the signal ø2 is temporarily set at “H” level andthe potential of the bit line BLk is transferred to the positive-phasenode N2.

[0349] At a time t7, the potential of the positive-phase node N2 and thepotential Vref of the anti-phase node /N2 are compared/amplified. If thepotential of the positive-phase node N2 is higher than the potentialVref of the anti-phase node /N2, it is determined that the bit data 2 is“0”. If the potential of the positive-phase node N2 is lower than thepotential Vref, it is determined that the bit data 2 is “1”. In responseto the determination of the bit data 2 as “0” or “1”, the potential ofthe source line SLk is changed. That is, when the bit data 2 is “0”, thepotential of the source line SLk remains 0V or Vm1. When the bit data 2is “1”, a positive potential Vm2 is further added to the potential ofthe source line SLk.

[0350] Further, in this embodiment, after the signal ø2 is turned from“H” level to “L” level, all the potentials of the select gate lines SG1and SG2, the select word line WL3 and the non-select word lines WL1, WL2and WL4 to WL8 are set at 0V.

[0351] At a time t8, while setting the potential of the source line SLkat 0V, Vm1, Vm2 or Vm1+Vm2, the potentials of the select gate lines SG1and SG2 are set at the potential Vread, that of the select word line WL3is set at a potential Vtc7 and those of the non-select word lines WL1,WL2 and WL4 to WL8 are set at the potential Vread. By doing so, thepotential of the bit line BLk is changed according to the thresholdvoltage of the memory cell MC3.

[0352] That is, as shown in FIG. 32C, if the threshold voltage of thememory cell MC3 is higher than a potential Vtc7, the memory cell MC3 isturned off and the potential of the bit line BLk substantially remainsthe potential Vpc. If the threshold voltage of the memory cell MC3 islower than the potential Vtc7, the memory cell is turned on and thepotential of the bit line BLk is lowered from the potential Vpc.

[0353] At a time t9, the signal ø3 is temporarily set at “H” level andthe potential of the bit line BLk is transferred to the positive-phasenode N3.

[0354] At a time t10, the potential of the positive-phase node N3 andthe potential Vref of the anti-phase node /N3 are compared/amplified. Ifthe potential of the positive-phase node N3 is higher than the potentialVref of the anti-phase node /N2, it is determined that the bit data 3 is“0”. If the potential of the positive-phase node N3 is lower than thepotential Vref, it is determined that the bit data 3 is “1”.

[0355] In this way, with the NAND type EEPROM shown in FIG. 29, theeight-level data stored in one memory cell can be converted to three-bitdata by carrying out data read three times.

[0356] (Fifth Embodiment)

[0357] There are two basic multilevel data reading techniques.

[0358] In the first technique, a bit line BL is pre-charged with “H”level and it is detected whether or not the pre-charged bit line BL isdischarged depending on whether the memory cell MC is turned on or off(which technique will be referred to as “bit line discharge technique”hereinafter).

[0359] In the second technique, the memory cell is turned on whilesetting a common line CL at “H” level and changing the bit line BL from“L” level to a floating state. Then, utilizing the variation of thecharge level of the bit line BL according to the threshold voltage ofthe memory cell MC, the reference potential is switched (n−1) times tothereby detect to which potential level the bit line BL is charged(which technique will be referred to as “threshold voltage detectiontechnique” hereinafter).

[0360] The shift of the threshold voltage due to the substrate biaseffect employed in the third and fourth embodiments occurs by changingthe potential of the terminal at a low potential of either the source ordrain of the MOSFET. The source potential of the memory cell isindividually set in the third and fourth embodiments, whereas thepotential of the bit line corresponding to the drain potential of thememory cell is individually set in this fifth embodiment.

[0361]FIG. 33 is a flowchart showing a four-level data reading method inthe fifth embodiment according to the present invention.

[0362] As shown in FIG. 33, data read is carried out twice as follows:

[0363] First Read:

[0364] While changing a bit line potential VBL from 0V to a floatingstate and setting the gate potential of a memory cell at a voltage Vtc2between “Vth10” and “Vth01”, data read is carried out. If the memorycell is turned “on” (Vtc2>Vth), data is either “11” or “10”. That is, itis determined that one of the two-bit data or bit data 1 in the fifthembodiment is “1”. If the memory cell is turned “off”, the data iseither “01” or “00”. That is, it is determined that the bit data 1 is“0”.

[0365] Second Read:

[0366] Before carrying out the second read, the bit line potential VBLis changed based on the result of the first read. That is, if the bitdata 1 is “1”, the bit line potential VBL is changed from the positivepotential Vm to a floating state. If the bit data 1 is “0”, the bit linepotential VBL is changed from 0V to a floating state as in the case ofthe first read.

[0367] If the potential VBL of the bit line BL is changed from thepositive potential Vm to the floating state, a positive potential Vm isadded to the reference potential Vref.

[0368] While the bit line potential VBL is set individually as statedabove and the gate potential is set at a read voltage Vtc3 between“Vth01” and “Vth00”, data read is carried out. If the memory cell isturned “on” (Vtc3>Vth), data is either “01” or “11”. That is, it isdetermined that the other data of the two-bit data or bit data 2 in thefifth embodiment is “1”. If the memory cell is turned “off”, the data iseither “00” or “01”. That is, it is determined that the bit data 2 is“0”.

[0369] According to the fifth embodiment as in the case of the thirdembodiment, the bit data 1 is determined in the first read and if thebit data 1 is “1”, the bit line potential VBL is changed from thepositive potential Vm to a floating state. Besides, the positivepotential Vm is added to the reference potential Vref. This makes itpossible to determine the bit data 2 in the second read in which thegate potential is fixed to Vtc3.

[0370] As a result, according to the fifth embodiment as in the case ofthe third embodiment, the four-level data stored in one memory cell canbe converted to two-bit data by carrying out data read twice.

[0371] According to the above-stated fifth embodiment, compared with theconventional threshold voltage detection technique in which thereference potential is switched (n−1) times and comparison/amplificationis carried out (n−1) times, it is possible to reduce the number ofcomparison/amplification operations to not less than m (where m is thelowest integer satisfying log₂n≦m) and less than (n−1). It is,therefore, possible to obtain the advantage of easily shortening timerequired from data read to data determination.

[0372]FIG. 34 is a block diagram showing an example of the configurationof an NAND type EEPROM to which the four-level data reading method inthe fifth embodiment according to the present invention is applied.

[0373] As shown in FIG. 34, the data line circuit 133 of the NAND typeEEPROM to which the four-level data reading method in the fifthembodiment according to the present invention is applied, includescharge/discharge circuits 137 (137 k, 137 k+1), data determinationcircuits 138 (138 k, 138 k+1) for determining data to be read on bitlines BL (BLk, BLk+1), a common line driving circuit 39 for driving acommon line CL shared among NAND cells 4 and reference potentialswitches 140 (140 k, 140 k+1).

[0374]FIG. 35 is a circuit diagram for the data determination circuit138 k. While the data determination circuit 138 k is shown in FIG. 35,the data determination circuit 138 k+1 is similar to the circuit 138 k.

[0375] As shown in FIG. 35, the data determination circuit 138 k hasalmost the same configuration as that of the data determination circuit108 k in the third embodiment. The data determination circuit 138differs from the circuit 108 k in that after bit data 1 is determinedwhile changing the potential of the bit line BL (BLk, BLk+1) from 0V toa floating state, bit data 2 is determined while changing the potentialof the bit line BL (BLk, BLk+1) from 0V to a floating state or from apositive potential Vm to a floating state according to the determinationresult of the bit data 1 and in that a positive potential Vm is added toa reference potential Vref.

[0376] In the determination of the bit data 2, whether or not thereference potential and the potential of the bit lines BL (BLk, BLk+1)are switched is determined based on the potential of the positive-phasenode N1 (or anti-phase node /N1) of the sense amplifier/data latchcircuit 110-1.

[0377] Next, the operation of the sense amplifier/data latch circuitwill be described. The following description of the operation is givenwhile paying attention to the bit line BLk and assuming that a word lineWL3 is selected.

[0378]FIG. 36 is a waveform view showing the operation of the NAND typeEEPROM shown in FIG. 34.

[0379] As shown in FIG. 36, at a time t0, the bit line BLk ispre-charged with 0V.

[0380] At a time t1, signals ø1 and ø2 are temporarily set at “H” leveland positive-phase nodes N1 and N2 are pre-charged with 0V.

[0381] At a time t2, while the potential of the bit line BLk is changedfrom 0V to a floating state and that of the common line CL is set at Vd,the potentials of select gate lines SG1 and SG2 are set at a potentialVread, that of the select word line WL3 is set at a potential Vtc2 andthose of non-select word lines WL1, WL2 and WL4 to WL8 are set at apotential Vread. By doing so, the potential of the bit line BLk ischanged according to the threshold voltage of the memory cell MC3. Thatis, if the threshold voltage of the memory cell MC3 is higher than thepotential Vtc2, the memory cell MC3 is turned off and the potential ofthe bit line BLk substantially remains 0V. If the threshold voltage ofthe memory cell MC3 is lower than the potential Vtc2, the memory cellMC3 is turned on and the potential of the bit line BLk is increased from0V to either “Vtc2−Vth10” or “Vtc2−Vth11” according to the thresholdvoltage of the memory cell.

[0382] At a time t3, the signal ø1 is temporarily set at “H” level andthe potential of the bit line BLk is transferred to the positive-phasenode N1.

[0383] At a time t4, the potential of the positive-phase node N1 and thepotential Vref of the anti-phase node /N1 are compared/amplified. If thepotential of the positive-phase node N1 is higher than the potentialVref of the anti-phase node /N1, it is determined that the bit data 1 is“1”. If the potential of the positive-phase node N1 is lower, it isdetermined that the bit data 1 is “0”. In response to the determinationof the bit data 1 as either “0” or “1”, the potential of the bit lineBLk and the reference potential Vref are changed. That is, if the bitdata 1 is “0”, the potential of the bit line BLk is changed to 0V. Ifthe bit data 1 is “1”, the potential of the bit line BLk is changed to apositive potential Vm and the positive potential Vm is added to thereference potential Vref.

[0384] In this embodiment, after the signal ø1 is changed from “H” levelto “L” level, all the potentials of the select gate lines SG1 and SG2,the select word line WL3 and the non-select word lines WL1, WL2 and WL4to WL8 are set at 0V.

[0385] At a time t5, while the potential of the bit line BLk is changedfrom 0V to a floating state or from the positive potential Vm to afloating state and that of the common line CL is set at Vd, thepotentials of the select gate lines SG1 and SG2 are set at the potentialVread, that of the select word line WL3 is set at the potential Vtc3 andthose of the non-select word lines WL1, WL2 and WL4 to WL8 are set atthe potential Vread. By doing so, the potential of the bit line BLk ischanged according to the threshold voltage of the memory cell MC3. Thatis, if the threshold voltage of the memory cell MC3 is higher than thepotential Vtc3, the memory cell MC3 is turned off and the potential ofthe bit line BLk substantially remains 0V or the positive potential Vm.If the threshold voltage of the memory cell MC3 is lower than thepotential Vtc3, the memory cell MC3 is turned on and the potential ofthe bit line BLk is increased by “Vtc3−Vth01”.

[0386] At a time t6, the signal ø2 is temporarily set at “H” level andthe potential of the bit line BLk is transferred to the positive-phasenode N2.

[0387] At a time t7, the potential of the positive-phase node N2 and thepotential Vref or Vref+Vm of the anti-phase node /N2 arecompared/amplified. If the potential of the positive-phase node N2 ishigher than the potential Vref or Vref+Vm of the anti-phase node /N2, itis determined that the bit data 2 is “1”. If the potential of thepositive-phase node N1 is lower than the potential Vref or Vref+Vm, itis determined that the bit data 2 is “0”.

[0388] As can be seen from the above, in the NAND type EEPROM shown inFIG. 34, the four-level data stored in one memory cell can be convertedto two-bit data by carrying out data read twice andcomparison/amplification twice.

[0389] (Sixth Embodiment)

[0390]FIG. 37 is a flowchart showing an eight-level data reading methodin the sixth embodiment according to the present invention.

[0391] As shown in FIG. 37, data read is carried out three times asfollows.

[0392] First Read:

[0393] While changing a bit line potential VBL from 0V to a floatingstate and setting the gate potential of a memory cell at a read voltageVtc4 between “Vth011” and “Vth100”, data read is carried out. If thememory cell is turned “on” (Vtc4>Vth), data is one of data “100”, “101”,“110” and “111”. That is, it is determined that one of the three-bitdata or bit data 1 in the sixth embodiment is “1”. If the memory cell isturned “off”, the data is one of data “000”, “001”, “010” and “011”.That is, it is determined that the bit data 1 is “0”.

[0394] Second Read:

[0395] Prior to carrying out the second read, the bit line potential VBLis changed based on the result of the first read. That is, if the bitdata 1 is “1”, the bit line potential VBL is changed from a positivepotential Vm1 to a floating state. If the bit data 1 is “0”, the bitline potential VBL is changed from 0V to a floating state as in the caseof the first read. If the bit data 1 is “1”, the positive potential Vm1is added to a reference potential Vref.

[0396] While the bit line potential VBL and the reference potential Vrefare individually set based on the result of the first read as statedabove and the gate potential is set at a voltage Vtc6 between “Vth010”and “Vth001”, data read is carried out. If the memory cell is turned“on” (Vtc6>Vth), data is one of data “010”, “011”, “110” and “111”. Thatis, it is determined that the second data of the three-bit data or bitdata 2 in the sixth embodiment is “1”. If the memory cell is turned“off”, the data is one of data “000”, “001”, “100” and “101”. That is,it is determined that the bit data 2 is “0”.

[0397] Third Read:

[0398] Prior to carrying out the third read, the bit line potential VBLis changed based on the result of the second read. That is, if the bitdata 2 is “1”, the positive potential Vm2 is added to the bit linepotential VBL and the potential VBL is changed to a floating state. Ifthe bit data 2 is “0”, the bit line potential VBL is changed from 0V orthe positive potential Vm to a floating state as in the case of thesecond read. If the bit data 2 is “1”, a positive potential Vm2 is addedto the reference potential Vref or Vref+Vm1.

[0399] While the bit line potential VBL and the reference potential Vrefare individually set as stated above and the gate potential is set at avoltage Vtc7 between “Vth001” and “Vth000”, data read is carried out. Ifthe memory cell is turned “on” (Vtc7>Vth), data is one of data “001”,“011”, “101” and “111”. That is, it is determined that the third data ofthe three-bit data or bit data 3 in the sixth embodiment is “1”. If thememory cell is turned “off”, the data is one of data “000”, “010”, “100”and “110”. That is, it is determined that the bit data 3 is “0”.

[0400] According to the above-stated sixth embodiment as in the case ofthe fourth embodiment, the bit data 1 is determined in the first readand if the bit data 1 thus determined is “1”, the bit line potential VBLis changed from the positive potential Vm1 to a floating state. Besides,the positive potential Vm1 is added to the reference potential Vref.This makes it possible to determine the bit data 2 in the second readwhile the gate potential is fixed to Vtc6. If the bit data 2 isdetermined as “1” in the second read, the bit line potential VBL ischanged from a potential to which the positive potential Vm2 is added toa floating state. Further, the positive potential Vm2 is added to thereference potential Vref or Vref+Vm1. This makes it possible todetermine the bit data 3 in the third read in which the gate potentialis fixed to Vtc7.

[0401] As a result, as in the case of the fourth embodiment, theeight-level data stored in one memory cell can be converted to three-bitdata by carrying out data read three times and comparison/amplificationthree times in the sixth embodiment.

[0402] Furthermore, according to the sixth embodiment as in the case ofthe fifth embodiment, compared with the conventional threshold voltagedetection technique for switching the reference potential (n−1) timesand conducting comparison/amplification (n−1) times, the number ofcomparison/amplification operations can be reduced to not less than m(where m is the lowest integer satisfying log₂n≦m) and less than (n−1).Thus, compared with the multilevel data reading method includingswitching the reference potential (n−1) times, the method in thisembodiment can obtain the advantage of easily shortening time requiredfor carrying out data read to data determination.

[0403]FIG. 38 is a block diagram showing an example of the configurationof the NAND type EEPROM to which the eight-level data reading method inthe sixth embodiment according to the present invention is applied.

[0404] As shown in FIG. 38, the EEPROM to which the sixth embodiment isapplied, differs from the EEPROM shown in FIG. 34 in the configurationof a data line circuit 133′. To be specific, bit line charge/dischargecircuits 137′ (137′k, 137′k+1) switch the bit line potentials VBL toeither 0V or the positive potential Vm1 according to the bit data 1.According to the bit data 2, the positive potential Vm2 is further addedto the bit line potentials VBL. The connection of a reference potentialswitch 140′k is controllable according to the bit data 1 and bit data 2.

[0405]FIG. 39 is a circuit diagram for a data determination circuit138′k shown in FIG. 38. While the data determination circuit 138′k isshown in FIG. 39, a data determination circuit 138′k+1 is similar to thecircuit 138′k.

[0406] As shown in FIG. 39, the data determination circuit 138′k hasalmost the same configuration as that of the data determination circuit8′k in the fourth embodiment. The differences of the circuit 138′k fromthe circuit 8′k are as follows. After the bit data 1 is determined whilechanging the potential of the bit line BL (BLk, BLk+1) from 0V to afloating state, the bit data 2 is determined while changing thepotential of the bit line BL (BLk, BLk+1) from 0V to a floating state orfrom the positive potential Vm1 to a floating state according to thedetermination result of the bit data 1. Also, the positive potential Vm1is added to the reference potential Vref.

[0407] Further, according to the determination result of the bit data 2,the potential of the bit line BL (BLk, BLk+1) is changed from 0V to afloating state, from the positive potential Vm1 to a floating state,from the positive potential Vm2 to a floating state or from the positivepotential Vm1+Vm2 to a floating state, and then the bit data 2 isdetermined. Also, the positive potential Vm2 is added to the referencepotential Vref or Vref+Vm1 to thereby set the reference potential at oneof Vref, Vref+Vm2, Vref+Vm1, Vref+Vm1+Vm2.

[0408] In the determination of the bit data 2, whether or not thepotential of the bit line BL (BLk, BLk+1) is switched and whether or notthe reference potential Vref or Vref+Vm1 is switched are determinedbased on the potential of the positive-phase node N1 (or anti-phase node/N1) of a sense amplifier/data latch circuit 110-1.

[0409] Also, in the determination of the bit data 3, whether or not thepotential of the bit line BL (BLk, BLk+1) is switched and whether or notthe reference potential Vref is switched are based on the potential ofthe positive-phase node N2 (or anti-phase node /N2) of a senseamplifier/data latch circuit 110-2.

[0410] Next, the operation of the sense amplifier/data latch circuitwill be described. It is noted that the following description of theoperation is given while paying attention to the bit line BLk andassuming that a word line WL3 is selected.

[0411]FIG. 40 is a waveform view showing the operation of the NAND typeEEPROM shown in FIG. 38.

[0412] As shown in FIG. 40, at a time t0, the bit line BLk ispre-charged with 0V.

[0413] At a time t1, signals ø1, ø2 and ø3 are temporarily set at “H”level and positive-phase nodes N1, N2 and N3 are pre-charged with 0V.

[0414] At a time t2, while the potential of the bit line BLk is changedfrom 0V to a floating state and the potential of a common line CL is setat Vd, the potentials of select gate lines SG1 and SG2 are set at apotential Vread, that of the select word line WL3 is set at a potentialVtc4 and those of non-select word lines WL1, WL2 and WL4 to WL8 are setat the potential Vread. By doing so, the potential of the bit line BLkis changed according to the threshold voltage of the memory cell MC3.That is, if the threshold voltage of the memory cell MC3 is higher thanthe potential Vtc4, the memory cell MC3 is turned off and the potentialof the bit line BLk substantially remains 0V. If the threshold voltageof the memory cell MC3 is lower than the potential Vtc4, the memory cellMC3 is turned on and the potential of the bit line BLk is increased from0V to one of “Vtc4-Vth100”, “Vtc4-Vth101”, “Vtc4-Vth110” and“Vtc4-Vth111” according to the threshold voltage of the memory cell.

[0415] At a time t3, the signal ø1 is temporarily set at “H” level andthe potential of the bit line BLk is transferred to the positive-phasenode N1.

[0416] At a time t4, the potential of the positive-phase node N1 and thepotential Vref of the anti-phase node /N1 are compared/amplified. If thepotential of the positive-phase node N1 is higher than the potentialVref of the anti-phase node /N1, it is determined that the bit data 1 is“1”. If the potential of the positive-phase node N1 is lower, it isdetermined that the bit data 1 is “0”. In response to the determinationof the bit data 1 as “0” or “1”, the potential of the bit line BLk ischanged. That is, when the bit data 1 is “0”, the potential of the bitline BLk is set at 0V. When the bit data 1 is “1”, the potential of thebit line BLk is changed to the positive potential Vm1. When the bit data1 is “1”, the positive potential Vm1 is added to the reference potentialVref.

[0417] In this embodiment, after the signal ø1 is changed from “H” levelto “L” level, all the potentials of the select gate lines SG1 and SG2,the select word line WL3 and the non-select word lines WL1, WL2 and WL4to WL8 are set at 0V.

[0418] At a time t5, while the potential of the bit line BLk is changedfrom 0V to a floating state or from the positive potential Vm1 to afloating state and that of the common line CL is set at Vd, thepotentials of the select gate lines SG1 and SG2 are set at the potentialVread, that of the select word line WL3 is set at a potential Vtc6 andthose of the non-select word lines WL1, WL2 and WL4 to WL8 are set atthe potential Vread. By doing so, the potential of the bit line BLk ischanged according to the threshold voltage of the memory cell MC3. Thatis, if the threshold voltage of the memory cell MC3 is higher than thepotential Vtc6, the memory cell MC3 is turned off and the potential ofthe bit line BLk substantially remains 0V or the positive potential Vm1.If the threshold voltage of the memory cell MC3 is lower than thepotential Vtc6, the memory cell MC3 is turned on and the potential ofthe bit line BLk is increased by “Vtc6-Vth010” or “Vtc6-Vth011”.

[0419] At a time t6, the signal ø2 is temporarily set at “H” level andthe potential of the bit line BLk is transferred to the positive-phasenode N2.

[0420] At a time t7, the potential of the positive-phase node N2 and thepotential Vref of the anti-phase node /N2 are compared/amplified. If thepotential of the positive-phase node N2 is higher than the potentialVref or Vref+Vm1 of the anti-phase node /N2, it is determined that thebit data 2 is “1”. If the potential of the positive-phase node N2 islower than the potential Vref or Vref+Vm1, it is determined that the bitdata 2 is “0”. In response to the determination of the bit data 2 as “0”or “1”, the potential of the bit line BLk and the reference potentialVref are changed. That is, when the bit data 2 is “0”, the potential ofthe bit line BLk is set at 0V or the positive potential Vm1. If the bitdata 1 is “1”, the positive potential Vm2 is added to the potential ofthe bit line BLk and also to the reference potential Vref.

[0421] In this embodiment, after the signal ø2 is changed from “H” levelto “L” level, all the potentials of the select gate lines SG1 and SG2,the select word line WL3 and the non-select word lines WL1, WL2 and WL4to WL8 are set at 0V.

[0422] At a time t8, while the potential of the bit line BLk is changedfrom 0V to a floating state, from the positive potential Vm2 to afloating state, from the positive potential Vm1 to a floating state orfrom the positive potential Vm1+Vm2 to a floating state and thepotential of the common line CL is set at Vd, the potentials of theselect gate lines SG1 and SG2 are set at the potential Vread, that ofthe select word line WL3 is set at a potential Vtc7 and those of thenon-select word lines WL1, WL2 and WL4 to WL8 are set at the potentialVread. By doing so, the potential of the bit line BLk is changedaccording to the threshold voltage of the memory cell MC3. That is, ifthe threshold voltage of the memory cell MC3 is higher than thepotential Vtc7, the memory cell MC3 is turned off and the potential ofthe bit line BLk substantially remains 0V, the positive potential Vm2,the positive potential Vm1 or the positive potential Vm1+Vm2. If thethreshold voltage of the memory cell MC3 is lower than the potentialVtc7, the memory cell MC3 is turned on and the potential of the bit lineBLk is increased by “Vtc7-Vth001”.

[0423] At a time t9, the signal ø3 is temporarily set at “H” level andthe potential of the bit line BLk is transferred to the positive-phasenode N3.

[0424] At a time t10, the potential of the positive-phase node N3 andthe potential Vref of the anti-phase node /N3 are compared/amplified. Ifthe potential of the positive-phase node N3 is higher than the potentialVref, Vref+Vm2, Vref+Vm1 or Vref+Vm1+Vm2 of the anti-phase node /N3, itis determined that the bit data 3 is “1”. If the potential of thepositive-phase node N3 is lower than the potential Vref, Vref+Vm2,Vref+Vm1 or Vref+Vm1+Vm2 of the anti-phase node /N3, it is determinedthat the bit data 3 is “0”.

[0425] In the NAND type EEPROM shown in FIG. 38 as stated above, theeight-level data stored in one memory cell can be converted to three-bitdata by carrying out data read three times and comparison/amplificationthree times.

[0426]FIG. 41 shows the relationship between the number of data levelsand the number of times of data read.

[0427] As shown in FIG. 41, according to the third to sixth embodiments,it is possible to reduce the number of times of data read necessary todetermine the number of data levels n from conventional (n−1) to notless than m (where m is the lowest integer satisfying log₂n=m) and lessthan (n−1). By reducing the number of times of data read, time requiredfor data read can be shortened.

[0428] Description has been given to the invention according to thethird to sixth embodiments. Needless to say, the present inventionshould not be limited to the third to sixth embodiments and may bemodified in various manners within the scope of the concept of thepresent invention.

[0429] For example, the third to sixth embodiments have illustrated theNAND type EEPROM. The present invention should not be limited to theNAND type EEPROM but may be applicable to other types of EEPROMincluding NOR type, DINOR type, AND type and the like.

[0430] The fourth and sixth embodiments have particularly illustrated acase where the potential supplied to the source line or bit line duringthe third read operation is obtained by adding the positive potentialVm2 to the positive potential Vm1 supplied to the source line or bitline during the second read operation. It is also possible to separatelyprepare a potential almost equal to the sum of the positive potentialsVm1 and Vm2 without adding the positive potential Vm2 and to supply thepotential to the source line or bit line by switching operation.

[0431] Likewise, the fifth and sixth embodiments have illustrated a casewhere the reference potential Vref is changed by adding thereto thepositive potential Vm, the positive potential Vm1 or the positivepotential Vm2. It is also possible that two types of referencepotentials and four types thereof are prepared in the second and fourthembodiments, respectively and that these reference potentials aresupplied to the sense amplifiers/latch circuits 10 (10-1 to 10-3) byswitching operation.

[0432] As stated so far, according to the invention in the first andsecond embodiments, in case of controlling the distribution of thethreshold voltages of the memory cells after data erase, soft eraseoperation for gradually shifting the threshold voltages in negativedirection is adopted. As a result, it is possible to greatly narrow thedistribution of threshold voltages after data erase even for the memorycell which has been miniaturized considerably. This makes it possible togreatly reduce chances of memory cell writing errors or thresholdvoltage variation during data write. It is possible to provide a highlyreliable nonvolatile semiconductor memory which is a binary ormultilevel memory miniaturized to not more than the rule of a gatelength of 0.25 μm.

[0433] According to the invention in the third to sixth embodiments, itis possible to shorten time required for reading data from a memory cellin a nonvolatile semiconductor memory having memory cells each of whichstores n-level (where n is an integer of not less than 4) data.

[0434] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A nonvolatile semiconductor memory devicecomprising: a memory section including at least one variable thresholdvoltage type memory cell, the variable threshold voltage type memorycell storing data according to a threshold voltage of the memory cell;and a signal line which transmits a potential related to data stored bythe variable threshold voltage type memory cell, wherein during a datastored in the memory cell is erased, a soft erase operation to graduallyshifted the threshold voltage of the memory cell in one of a negativedirection or a positive direction is carried out.
 2. A nonvolatilesemiconductor memory device comprising: a memory section including atleast one variable threshold voltage type memory cell, the variablethreshold voltage type memory cell storing data according to a thresholdvoltage of the memory cell; and a signal line which transmits apotential related to data stored by the variable threshold voltage typememory cell, wherein during a data stored in the memory cell is erased,a soft erase operation to gradually shifted the threshold voltage of thememory cell in one direction of a negative or a positive and a softwrite operation to gradually shifted the threshold voltage of the memorycell in opposite direction to the one direction are carried out.
 3. Thenonvolatile semiconductor memory device according to claim 1, whereinafter the soft erase operation, a verification operation to verified thethreshold voltage of the memory cell is carried out and whether or notto repeat the soft erase operation is determined based on a result ofthe verification operation.
 4. The nonvolatile semiconductor memorydevice according to claim 2, wherein after the soft erase operation, averification operation to verified the threshold voltage of the memorycell is carried out and whether or not to repeat the soft eraseoperation is determined based on a result of the verification operation.5. The nonvolatile semiconductor memory device according to claim 2,wherein after the soft write operation, a verification operation toverified the threshold voltage of the memory cell is carried out andwhether or not to repeat the soft write operation is determined based ona result of the verification operation.
 6. A nonvolatile semiconductormemory device comprising: a memory cell unit including a plurality ofvariable threshold voltage type memory cells, the variable thresholdvoltage type memory cells storing data according to threshold voltagesof the variable threshold voltage type memory cells, respectively; amemory cell array including a block constituted by arranging a pluralityof the memory cell units; a first signal line which receives a potentialat one end of the memory cell unit and transmits potentials related todata stored by the variable -threshold voltage type memory cells; and asecond signal line which supplies a potential to another end of thememory cell unit, wherein during a data stored in the memory cells iserased, a soft erase operation to gradually shifted the thresholdvoltages of the memory cells in one of a negative direction or apositive direction and a verification operation to verified thethreshold voltages of the memory cells are repeatedly carried out foreach block.
 7. The nonvolatile semiconductor memory device according toclaim 6, wherein the soft erase operation is carried out by means of astep-up technique for increasing a control voltage to shifted thethreshold voltages of the memory cells in the negative direction, from astart voltage by a predetermined step width; and when it is detectedthat the threshold voltages of all of the memory cells in the block arelower than a reference value during the verification operation, the softerase operation is ended.
 8. A nonvolatile semiconductor memory devicecomprising: a memory cell unit including a plurality of variablethreshold voltage type memory cells, the variable threshold voltage typememory cells storing data according to threshold voltages of thevariable threshold voltage type memory cells, respectively; a memorycell array including a block constituted by arranging a plurality of thememory cell units; a first signal line which receives a potential at oneend of the memory cell unit and transmits potentials related to datastored by the variable threshold voltage type memory cells; and a secondsignal line which supplies a potential to another end of the memory cellunit, wherein during a data stored in the memory cells is erased, a softerase operation to gradually shifted the threshold voltage of the memorycell in one direction of a negative or a positive, a soft eraseoperation to gradually shifted the threshold voltages of the memorycells in the negative direction and a first verification operation toverified the threshold voltages of the memory cells are repeatedlycarried out for each block; and after the soft erase operation is ended,a soft write operation to gradually shifted the threshold voltages ofthe memory cells in opposite direction to the one direction and a secondverification operation to verified the threshold voltages of the memorycells are repeatedly carried out.
 9. The nonvolatile semiconductormemory device according to claim 8, wherein the soft erase operation iscarried out by means of a step-up technique for increasing a firstcontrol voltage to shifted the threshold voltages of the memory cells inthe negative direction, from a start voltage by a predetermined stepwidth; in the first verification operation, when it is determined thatthe threshold voltages of all of the memory cells in the block are lowerthan a first reference value, the soft erase operation is ended; thesoft write operation is carried out by means of a step-up technique forincreasing a second control voltage to shifted the threshold voltages ofthe memory cells in the positive direction, from a start voltage by apredetermined step width; and in the second verification operation, whenit is detected that the threshold voltages of all of the memory cells inthe block are higher than a second reference value, the soft writeoperation is ended.
 10. The nonvolatile semiconductor memory deviceaccording to claim 1, wherein before the soft erase operation, a dataprewrite operation to shifted the threshold voltage of the memory cellin the positive direction is carried out.
 11. The nonvolatilesemiconductor memory device according to claim 2, wherein before thesoft erase operation, a data prewrite operation to shifted the thresholdvoltage of the memory cell in the positive direction is carried out. 12.The nonvolatile semiconductor memory device according to claim 6,wherein before the soft erase operation, a data prewrite operation toshifted the threshold voltages of the memory cells in the positivedirection is carried out.
 13. The nonvolatile semiconductor memorydevice according to claim 8, wherein before the soft erase operation, adata prewrite operation to shifted the threshold voltages of the memorycells in the positive direction is carried out.
 14. The nonvolatilesemiconductor memory device according to claim 1, wherein a plurality ofthe memory cells are connected in series and constitute an NAND typecell; during a data write operation carried out after the data eraseoperation, a write voltage is applied to a control gate of a selectedmemory cell in the NAND cell; a first voltage lower than the writevoltage is applied to control gates of the memory cells adjacent to theselected memory cell; and a second voltage lower than the write voltageand higher than the first voltage is applied to control gates of thememory cells except for the selected memory cell and the adjacent memorycells.
 15. The nonvolatile semiconductor memory device according toclaim 2, wherein a plurality of the memory cells are connected inseries; during a data write operation carried out after the data eraseoperation, a write voltage is applied to a control gate of a selectedmemory cell in the NAND cell; a first voltage lower than the writevoltage is applied to control gates of the memory cells adjacent to theselected memory cell; and a second voltage lower than the write voltageand higher than the first voltage is applied to control gates of thememory cells except for the selected memory cell and the adjacent memorycells.
 16. The nonvolatile semiconductor memory device according toclaim 6, wherein a plurality of the memory cells are connected in seriesbetween the first signal line and the second signal line and constitutean NAND type cell; during a data write operation carried out after thedata erase operation, a write voltage is applied to a control gate of aselected memory cell in the NAND cell; a first voltage lower than thewrite voltage is applied to control gates of the memory cells adjacentto the selected memory cell; and a second voltage lower than the writevoltage and higher than the first voltage is applied to control gates ofthe memory cells except for the selected memory cell and the adjacentmemory cells.
 17. The nonvolatile semiconductor memory device accordingto claim 8, wherein a plurality of the memory cells are connected inseries between the first signal line and the second signal line andconstitute an NAND type cell; during a data write operation carried outafter the data erase operation, a write voltage is applied to a controlgate of a selected memory cell in the NAND cell; a first voltage lowerthan the write voltage is applied to control gates of the memory cellsadjacent to the selected memory cell; and a second voltage lower thanthe write voltage and higher than the first voltage is applied tocontrol gates of the memory cells except for the selected memory celland the adjacent memory cells.
 18. A nonvolatile semiconductor devicecomprising: a memory cell array including at least first and secondmemory cells each storing n-level data, where n is an integer not lessthan 4; a first wiring which applies a source potential to the firstmemory cell; and a second wiring which applies a source potential to thesecond memory cell, wherein when determining the n-level data, read ofthe n-level data is divided into not less than m and less than (n−1)data read operations, where m is a lowest integer satisfying log₂n≦m;among the divided data read operations, a first data read operation iscarried out while setting the source potentials of the first and secondmemory cells at a common potential; and a second data read operationfollowing the first data read operation is carried out according to aresult of the first data read operation while individually setting thesource potentials of the first and second memory cells.
 19. Anonvolatile semiconductor device comprising: a first source line drivingcircuit; a first data determination circuit; a first memory cell whichstores n-level data, where n is an integer not less than 4, the firstmemory cell located between the first source line driving circuit andthe first data determination circuit; a second source line drivingcircuit; a second data determination circuit; and a second memory cellwhich stores n-level data, where n is an integer not less than 4, thesecond memory cell located between the second source line drivingcircuit and the second data determination circuit, wherein whendetermining the n-level data, read of the n-level data is divided intonot less than m and less than (n−1) data read operations, where m is asmallest integer satisfying log₂n≦m; among the divided data readoperations, during a first data read operation, the first and secondsource line driving circuits supply a common potential to sources of thefirst and second memory cells; and during a second data read operationfollowing the first data read operation, the first and second sourceline driving circuits supply individual potentials to sources of thefirst and second memory cells according to a determination result of thefirst data read operation carried out by the first and second datadetermination circuits.
 20. A nonvolatile semiconductor memory devicecomprising: a memory cell array including at least first and secondmemory cells each storing n-level data, where n is an integer not lessthan 4; a first data determination circuit which determines the n-leveldata stored by the first memory cell, the first data determinationcircuit associated with the first memory cell through a first signalline; a second data determination circuit which determines the n-leveldata stored by the second memory cell, the second data determinationcircuit associated with the second memory cell through a second signalline; a first charge/discharge circuit which charges and discharges thefirst signal line; and a second charge/discharge circuit which chargesand discharges the second signal line, wherein when determining then-level data, read of the n-level data is divided into not less than mand less than (n−1) data read operations, where m is a lowest integersatisfying log₂n≦m; among the divided data read operations, during afirst data read operation, the first and second charge/dischargecircuits set potentials of the first and second signal lines at a commonpotential; during a second data read operation following the first dataread operation, the first and second charge/discharge circuits setpotentials of the first and second signal lines at individualpotentials, according to a determination result of the first data readoperation carried out by the first and second data determinationcircuits.
 21. A nonvolatile semiconductor memory device comprising: amemory cell array including at least first and second memory cells eachstoring n-level data, where n is an integer not less than 4; a firstdata determination circuit which determines the n-level data stored bythe first memory cell; and a second data determination circuit whichdetermines the n-level data stored by the second memory cell, whereinwhen determining the n-level data, read of the n-level data is dividedinto not more than m and less than (n−1) data read operations, where mis a smallest integer satisfying log₂n≦m; among the divided data readoperations, during a first data read operation, reference potentials ofthe first and second data determination circuits are set at a commonfirst potential; and during a second data read operation following thefirst data read operation, the reference potentials of the first andsecond data determination circuits are set at the first potential or asecond potential different from the first potential, respectively,according to a result of the first data read operation.
 22. Anonvolatile semiconductor memory device according to claim 18, whereineach of the first and second read operations is carried out whilesetting gate potentials of the first and second memory cells at a commongate potential.
 23. A nonvolatile semiconductor memory device accordingto claim 19, wherein each of the first and second read operations iscarried out while setting gate potentials of the first and second memorycells at a common gate potential.
 24. A nonvolatile semiconductor memorydevice according to claim 20, wherein each of the first and second readoperations is carried out while setting gate potentials of the first andsecond memory cells at a common gate potential.
 25. A nonvolatilesemiconductor memory device according to claim 21, wherein each of thefirst and second read operations is carried out while setting gatepotentials of the first and second memory cells at a common gatepotential.